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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 09:58:33 +02:00
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ef710eae7aab2dcba4a415f8bd0ce52d31971580
OpenRAM/compiler/sram
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samuelkcrow ef710eae7a reorder sram __init__() argument order for tests that rely on the order
2022-03-04 13:53:20 -08:00
..
sram_1bank.py
Add extra dnwell spacing for single port
2021-06-23 11:14:58 -07:00
sram_2bank.py
Update copyright year.
2021-01-22 11:23:28 -08:00
sram_base.py
Initial work on separate delay and func simulation
2022-03-04 13:47:09 -08:00
sram_config.py
Initial work on separate delay and func simulation
2022-03-04 13:47:09 -08:00
sram.py
reorder sram __init__() argument order for tests that rely on the order
2022-03-04 13:53:20 -08:00
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