mirror of https://github.com/VLSIDA/OpenRAM.git
52 lines
1.3 KiB
Python
52 lines
1.3 KiB
Python
#!/usr/bin/env python2.7
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"""
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Run a regresion test on a control_logic
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"""
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import unittest
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from testutils import header
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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import verify
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class control_logic_test(unittest.TestCase):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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# we will manually run lvs/drc
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OPTS.check_lvsdrc = False
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import control_logic
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import tech
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debug.info(1, "Testing sample for control_logic")
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a = control_logic.control_logic(num_rows=128)
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self.local_check(a)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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def local_check(self, a):
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tempspice = OPTS.openram_temp + "temp.sp"
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tempgds = OPTS.openram_temp + "temp.gds"
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a.sp_write(tempspice)
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a.gds_write(tempgds)
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self.assertFalse(verify.run_drc(a.name, tempgds))
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self.assertFalse(verify.run_lvs(a.name, tempgds, tempspice))
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os.remove(tempspice)
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os.remove(tempgds)
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# instantiate a copdsay of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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