mirror of https://github.com/VLSIDA/OpenRAM.git
126 lines
4.4 KiB
Python
126 lines
4.4 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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from vector import vector
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import pgate
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from sram_factory import factory
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class pbuf_dec(pgate.pgate):
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"""
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This is a simple buffer used for driving wordlines.
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"""
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def __init__(self, name, size=4, height=None):
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debug.info(1, "creating {0} with size of {1}".format(name, size))
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self.add_comment("size: {}".format(size))
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self.stage_effort = 4
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self.size = size
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self.height = height
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# Creates the netlist and layout
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pgate.pgate.__init__(self, name, height)
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def create_netlist(self):
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self.add_pins()
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self.create_modules()
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self.create_insts()
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def create_layout(self):
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self.width = self.inv1.width + self.inv2.width
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self.place_insts()
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self.add_wires()
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self.add_layout_pins()
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self.route_supply_rails()
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self.add_boundary()
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def add_pins(self):
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self.add_pin("A", "INPUT")
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self.add_pin("Z", "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_modules(self):
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# Shield the cap, but have at least a stage effort of 4
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input_size = max(1, int(self.size / self.stage_effort))
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self.inv1 = factory.create(module_type="pinv_dec",
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size=input_size,
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height=self.height)
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self.add_mod(self.inv1)
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self.inv2 = factory.create(module_type="pinv_dec",
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size=self.size,
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height=self.height)
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self.add_mod(self.inv2)
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def create_insts(self):
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self.inv1_inst = self.add_inst(name="buf_inv1",
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mod=self.inv1)
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self.connect_inst(["A", "zb_int", "vdd", "gnd"])
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self.inv2_inst = self.add_inst(name="buf_inv2",
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mod=self.inv2)
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self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
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def place_insts(self):
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# Add INV1 to the right
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self.inv1_inst.place(vector(0, 0))
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# Add INV2 to the right
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self.inv2_inst.place(vector(self.inv1_inst.rx(), 0))
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def add_wires(self):
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# inv1 Z to inv2 A
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z1_pin = self.inv1_inst.get_pin("Z")
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a2_pin = self.inv2_inst.get_pin("A")
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mid_loc = vector(a2_pin.cx(), z1_pin.cy())
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self.add_path(self.route_layer,
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[z1_pin.rc(), mid_loc, a2_pin.lc()],
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width=a2_pin.width())
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def route_supply_rails(self):
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""" Add vdd/gnd rails to the top, (middle), and bottom. """
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self.copy_layout_pin(self.inv1_inst, "vdd")
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self.copy_layout_pin(self.inv1_inst, "gnd")
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self.copy_layout_pin(self.inv2_inst, "vdd")
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self.copy_layout_pin(self.inv2_inst, "gnd")
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def add_layout_pins(self):
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z_pin = self.inv2_inst.get_pin("Z")
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self.add_layout_pin_rect_center(text="Z",
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layer=z_pin.layer,
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offset=z_pin.center(),
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width=z_pin.width(),
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height=z_pin.height())
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a_pin = self.inv1_inst.get_pin("A")
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self.add_layout_pin_rect_center(text="A",
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layer=a_pin.layer,
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offset=a_pin.center(),
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width=a_pin.width(),
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height=a_pin.height())
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def get_stage_efforts(self, external_cout, inp_is_rise=False):
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"""Get the stage efforts of the A -> Z path"""
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stage_effort_list = []
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stage1_cout = self.inv2.get_cin()
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stage1 = self.inv1.get_stage_effort(stage1_cout, inp_is_rise)
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stage_effort_list.append(stage1)
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last_stage_is_rise = stage1.is_rise
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stage2 = self.inv2.get_stage_effort(external_cout, last_stage_is_rise)
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stage_effort_list.append(stage2)
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return stage_effort_list
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def get_cin(self):
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"""Returns the relative capacitance of the input"""
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input_cin = self.inv1.get_cin()
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return input_cin
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