mirror of https://github.com/VLSIDA/OpenRAM.git
94 lines
4.4 KiB
Python
94 lines
4.4 KiB
Python
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California
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# All rights reserved.
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#
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from openram import debug
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from openram.modules import bitcell_array
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from openram.sram_factory import factory
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from openram import OPTS
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from .sky130_bitcell_base_array import sky130_bitcell_base_array
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class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
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"""
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Creates a rows x cols array of memory cells.
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Assumes bit-lines and word lines are connected by abutment.
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"""
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def __init__(self, rows, cols, column_offset=0, name=""):
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# Don't call the regular bitcell_array constructor since we don't want its constructor, just
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# some of it's useful member functions
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sky130_bitcell_base_array.__init__(self, rows=rows, cols=cols, column_offset=column_offset, name=name)
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if self.row_size % 2 == 0:
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debug.error("Invalid number of rows {}. number of rows (excluding dummy rows) must be odd to connect to col ends".format(self.row_size), -1)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, self.row_size, self.column_size))
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self.add_comment("rows: {0} cols: {1}".format(self.row_size, self.column_size))
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# This will create a default set of bitline/wordline names
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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self.add_supply_pins()
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def add_modules(self):
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""" Add the modules used in this design """
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# Bitcell for port names only
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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self.cell2 = factory.create(module_type=OPTS.bitcell, version="opt1a")
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self.strap = factory.create(module_type="internal", version="wlstrap")
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self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
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self.strap3 = factory.create(module_type="internal", version="wlstrapa")
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self.strap4 = factory.create(module_type="internal", version="wlstrapa_p")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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self.array_layout = []
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alternate_bitcell = (self.row_size) % 2
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for row in range(0, self.row_size):
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row_layout = []
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alternate_strap = (self.row_size+1) % 2
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for col in range(0, self.column_size):
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if alternate_bitcell == 1:
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row_layout.append(self.cell)
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self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
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mod=self.cell)
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else:
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row_layout.append(self.cell2)
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self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
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mod=self.cell2)
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self.connect_inst(self.get_bitcell_pins(row, col))
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if col != self.column_size - 1:
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if alternate_strap:
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if row % 2:
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name="row_{}_col_{}_wlstrapa_p".format(row, col)
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row_layout.append(self.strap4)
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self.add_inst(name=name, mod=self.strap4)
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else:
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name="row_{}_col_{}_wlstrap_p".format(row, col)
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row_layout.append(self.strap2)
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self.add_inst(name=name, mod=self.strap2)
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alternate_strap = 0
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else:
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if row % 2:
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name="row_{}_col_{}_wlstrapa".format(row, col)
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row_layout.append(self.strap3)
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self.add_inst(name=name.format(row, col), mod=self.strap3)
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else:
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name="row_{}_col_{}_wlstrap".format(row, col)
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row_layout.append(self.strap)
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self.add_inst(name=name.format(row, col), mod=self.strap)
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alternate_strap = 1
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self.connect_inst(self.get_strap_pins(row, col, name))
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if alternate_bitcell == 0:
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alternate_bitcell = 1
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else:
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alternate_bitcell = 0
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self.array_layout.append(row_layout)
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