mirror of https://github.com/VLSIDA/OpenRAM.git
316 lines
13 KiB
Python
316 lines
13 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram import debug
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from openram.base import vector
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from openram.sram_factory import factory
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from openram.tech import layer_properties as layer_props
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from openram import OPTS
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from .bitcell_base_array import bitcell_base_array
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class local_bitcell_array(bitcell_base_array):
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"""
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A local bitcell array is a bitcell array with a wordline driver.
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This can either be a single aray on its own if there is no hierarchical WL
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or it can be combined into a larger array with hierarchical WL.
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"""
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def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
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super().__init__(name=name, rows=rows, cols=cols, column_offset=0)
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debug.info(2, "Creating {0} {1}x{2} rbl: {3} left_rbl: {4} right_rbl: {5}".format(name,
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rows,
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cols,
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rbl,
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left_rbl,
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right_rbl))
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self.rows = rows
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self.cols = cols
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# This is how many RBLs are in all the arrays
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self.rbl = rbl
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# This specifies which RBL to put on the left or right by port number
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# This could be an empty list
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if left_rbl is not None:
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self.left_rbl = left_rbl
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else:
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self.left_rbl = []
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# This could be an empty list
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if right_rbl is not None:
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self.right_rbl = right_rbl
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else:
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self.right_rbl=[]
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debug.check(len(self.all_ports) < 3, "Local bitcell array only supports dual port or less.")
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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# We don't offset this because we need to align
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# the replica bitcell in the control logic
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# self.offset_all_coordinates()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place()
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self.add_layout_pins()
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self.route()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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# This is just used for names
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self.cell = factory.create(module_type=OPTS.bitcell)
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self.bitcell_array = factory.create(module_type="capped_replica_bitcell_array",
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cols=self.cols,
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rows=self.rows,
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rbl=self.rbl,
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left_rbl=self.left_rbl,
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right_rbl=self.right_rbl)
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self.wl_array = factory.create(module_type="wordline_buffer_array",
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rows=self.rows + 1,
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cols=self.cols)
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def add_pins(self):
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# Outputs from the wordline driver (by port)
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self.driver_wordline_outputs = []
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# Inputs to the bitcell array (by port)
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self.array_wordline_inputs = []
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self.wordline_names = self.bitcell_array.wordline_names
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self.all_wordline_names = self.bitcell_array.all_wordline_names
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self.bitline_names = self.bitcell_array.bitline_names
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self.all_bitline_names = self.bitcell_array.all_bitline_names
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self.rbl_wordline_names = self.bitcell_array.rbl_wordline_names
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self.all_rbl_wordline_names = self.bitcell_array.all_rbl_wordline_names
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self.rbl_bitline_names = self.bitcell_array.rbl_bitline_names
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self.all_rbl_bitline_names = self.bitcell_array.all_rbl_bitline_names
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self.all_array_wordline_inputs = [x + "i" for x in self.bitcell_array.get_all_wordline_names()]
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# Arrays are always:
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# bit lines (left to right)
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# word lines (bottom to top)
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# vdd
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# gnd
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for port in self.left_rbl:
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self.add_pin_list(self.rbl_bitline_names[port], "INOUT")
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self.add_pin_list(self.all_bitline_names, "INOUT")
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for port in self.right_rbl:
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self.add_pin_list(self.rbl_bitline_names[port], "INOUT")
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for port in range(self.rbl[0]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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for port in self.all_ports:
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self.add_pin_list(self.wordline_names[port], "INPUT")
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for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.wl_insts = []
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self.driver_wordline_outputs = []
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for port in self.all_ports:
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self.wl_insts.append(self.add_inst(name="wl_driver{}".format(port),
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mod=self.wl_array))
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temp = []
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temp += [self.get_rbl_wordline_names(port)[port]]
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if port == 0:
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temp += self.get_wordline_names(port)
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else:
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temp += self.get_wordline_names(port)[::-1]
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self.driver_wordline_outputs.append([x + "i" for x in temp])
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temp += self.driver_wordline_outputs[-1]
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temp += ["vdd", "gnd"]
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self.connect_inst(temp)
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self.bitcell_array_inst = self.add_inst(name="array",
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mod=self.bitcell_array)
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temp = []
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for port in self.left_rbl:
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temp += self.get_rbl_bitline_names(port)
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temp += self.all_bitline_names
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for port in self.right_rbl:
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temp += self.get_rbl_bitline_names(port)
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wl_temp = []
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for port in range(self.rbl[0]):
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wl_temp += [self.get_rbl_wordline_names(port)[port]]
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wl_temp += self.get_wordline_names()
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for port in range(self.rbl[0], sum(self.rbl)):
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wl_temp += [self.get_rbl_wordline_names(port)[port]]
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temp += [x + "i" for x in wl_temp]
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temp += ["vdd", "gnd"]
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self.connect_inst(temp)
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def place(self):
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""" Place the bitcelll array to the right of the wl driver. """
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# FIXME: Replace this with a tech specific parameter
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driver_to_array_spacing = 3 * self.m3_pitch
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wl_offset = vector(0, self.bitcell_array.get_replica_bottom())
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self.wl_insts[0].place(wl_offset)
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bitcell_array_offset = vector(self.wl_insts[0].rx() + driver_to_array_spacing, 0)
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self.bitcell_array_inst.place(bitcell_array_offset)
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if len(self.all_ports) > 1:
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wl_offset = vector(self.bitcell_array_inst.rx() + self.wl_array.width + driver_to_array_spacing,
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self.bitcell_array.get_replica_bottom() + self.wl_array.height + self.cell.height)
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self.wl_insts[1].place(wl_offset,
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mirror="XY")
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self.height = self.bitcell_array.height
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self.width = max(self.bitcell_array_inst.rx(), max([x.rx() for x in self.wl_insts]))
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def add_layout_pins(self):
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for x in self.get_inouts():
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self.copy_layout_pin(self.bitcell_array_inst, x)
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supply_insts = [*self.wl_insts, self.bitcell_array_inst]
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for pin_name in ["vdd", "gnd"]:
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for inst in supply_insts:
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pin_list = inst.get_pins(pin_name)
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for pin in pin_list:
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self.copy_power_pin(pin)
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def route(self):
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global_wl_layer = layer_props.global_bitcell_array.wordline_layer
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global_wl_pitch = getattr(self, "{}_pitch".format(global_wl_layer))
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global_wl_pitch_factor = layer_props.global_bitcell_array.wordline_pitch_factor
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local_wl_layer = layer_props.local_bitcell_array.wordline_layer
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# Route the global wordlines
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for port in self.all_ports:
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if port == 0:
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wordline_names = [self.get_rbl_wordline_names(port)[port]] + self.get_wordline_names(port)
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else:
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wordline_names = [self.get_rbl_wordline_names(port)[port]] + self.get_wordline_names(port)[::-1]
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wordline_pins = self.wl_array.get_inputs()
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for (wl_name, in_pin_name) in zip(wordline_names, wordline_pins):
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# wl_pin = self.bitcell_array_inst.get_pin(wl_name)
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in_pin = self.wl_insts[port].get_pin(in_pin_name)
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y_offset = in_pin.cy()
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if port == 0:
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y_offset -= global_wl_pitch_factor * global_wl_pitch
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else:
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y_offset += global_wl_pitch_factor * global_wl_pitch
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mid = vector(in_pin.cx(), y_offset)
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self.add_layout_pin_rect_center(text=wl_name,
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layer=global_wl_layer,
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offset=mid)
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self.add_path(local_wl_layer, [in_pin.center(), mid])
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# A short jog to the global line
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self.add_via_stack_center(from_layer=in_pin.layer,
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to_layer=local_wl_layer,
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offset=in_pin.center(),
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min_area=True)
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self.add_path(local_wl_layer, [in_pin.center(), mid])
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self.add_via_stack_center(from_layer=local_wl_layer,
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to_layer=global_wl_layer,
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offset=mid,
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min_area=True)
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# Add the global WL pin
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self.add_layout_pin_rect_center(text=wl_name,
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layer=global_wl_layer,
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offset=mid)
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# Route the buffers
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for port in self.all_ports:
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driver_outputs = self.driver_wordline_outputs[port]
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for (driver_name, net_name) in zip(self.wl_insts[port].mod.get_outputs(), driver_outputs):
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array_name = net_name[:-1]
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out_pin = self.wl_insts[port].get_pin(driver_name)
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in_pin = self.bitcell_array_inst.get_pin(array_name)
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if port == 0:
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out_loc = out_pin.rc()
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mid_loc = vector(self.wl_insts[port].rx() + 1.5 * self.m3_pitch, out_loc.y)
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in_loc = in_pin.lc()
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else:
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out_loc = out_pin.lc()
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mid_loc = vector(self.wl_insts[port].lx() - 1.5 * self.m3_pitch, out_loc.y)
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in_loc = in_pin.rc()
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self.add_path(out_pin.layer, [out_loc, mid_loc])
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self.add_via_stack_center(from_layer=out_pin.layer,
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to_layer=in_pin.layer,
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offset=mid_loc)
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self.add_path(in_pin.layer, [mid_loc, in_loc])
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def get_main_array_top(self):
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return self.bitcell_array_inst.by() + self.bitcell_array.get_main_array_top()
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def get_main_array_bottom(self):
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return self.bitcell_array_inst.by() + self.bitcell_array.get_main_array_bottom()
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def get_main_array_left(self):
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return self.bitcell_array_inst.lx() + self.bitcell_array.get_main_array_left()
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def get_main_array_right(self):
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return self.bitcell_array_inst.lx() + self.bitcell_array.get_main_array_right()
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def get_column_offsets(self):
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"""
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Return an array of the x offsets of all the regular bits
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"""
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# must add the offset of the instance
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offsets = [self.bitcell_array_inst.lx() + x for x in self.bitcell_array.get_column_offsets()]
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return offsets
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def graph_exclude_bits(self, targ_row=None, targ_col=None):
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"""
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Excludes bits in column from being added to graph except target
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"""
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self.bitcell_array.graph_exclude_bits(targ_row, targ_col)
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def graph_exclude_replica_col_bits(self):
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"""
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Exclude all but replica in the local array.
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"""
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self.bitcell_array.graph_exclude_replica_col_bits()
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def get_cell_name(self, inst_name, row, col):
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"""Gets the spice name of the target bitcell."""
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return self.bitcell_array.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.bitcell_array_inst.name, row, col)
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def clear_exclude_bits(self):
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"""
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Clears the bit exclusions
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"""
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self.bitcell_array.clear_exclude_bits()
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