Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
eb2304944b47fd256757ffe7498f2ae2bece25de
OpenRAM/compiler/router
T
History
Matt Guthaus 12cb02a09f Add partial grids as pins. Add previous paths as routing targets.
2018-10-05 08:39:28 -07:00
..
tests
Add partial grids as pins. Add previous paths as routing targets.
2018-10-05 08:39:28 -07:00
direction.py
Routing and connecting rails with vias done.
2018-09-07 14:46:58 -07:00
grid_cell.py
Supply router working except:
2018-09-18 12:57:39 -07:00
grid_path.py
Routing and connecting rails with vias done.
2018-09-07 14:46:58 -07:00
grid.py
Cleanup of router.
2018-10-04 14:04:29 -07:00
router.py
Add partial grids as pins. Add previous paths as routing targets.
2018-10-05 08:39:28 -07:00
signal_grid.py
Supply router working except:
2018-09-18 12:57:39 -07:00
signal_router.py
Cleanup of router.
2018-10-04 14:04:29 -07:00
supply_grid.py
Supply router working except:
2018-09-18 12:57:39 -07:00
supply_router.py
Add partial grids as pins. Add previous paths as routing targets.
2018-10-05 08:39:28 -07:00
vector3d.py
DRC clean supply grid routing on control logic.
2018-09-20 16:00:13 -07:00
Powered by Gitea Version: 1.27.2 Page: 93ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API