mirror of https://github.com/VLSIDA/OpenRAM.git
54 lines
1.5 KiB
Python
Executable File
54 lines
1.5 KiB
Python
Executable File
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import sys, os
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import unittest
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from testutils import *
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import openram
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from openram import debug
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from openram.sram_factory import factory
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from openram import OPTS
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class and2_dec_test(openram_test):
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def runTest(self):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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openram.init_openram(config_file, is_unit_test=True)
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#global verify
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from openram import verify
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 0
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openram.setup_bitcell()
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debug.info(2, "Testing and2_dec 1rw/1r gate")
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a = factory.create(module_type="and2_dec")
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self.local_check(a)
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 0
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OPTS.num_w_ports = 0
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openram.setup_bitcell()
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debug.info(2, "Testing and2_dec 1rw gate")
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a = factory.create(module_type="and2_dec")
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self.local_check(a)
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openram.end_openram()
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# instantiate a copdsay of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = openram.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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