mirror of https://github.com/VLSIDA/OpenRAM.git
176 lines
6.9 KiB
Python
176 lines
6.9 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import os
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import shutil
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import datetime
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from openram import debug
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from openram import rom_config as config
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from openram import OPTS, print_time
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class rom():
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"""
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This is not a design module, but contains an ROM design instance.
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"""
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def __init__(self, rom_config=None, name=None):
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# Create default configs if custom config isn't provided
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if rom_config is None:
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rom_config = config(rom_data=OPTS.rom_data,
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word_size=OPTS.word_size,
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words_per_row=OPTS.words_per_row,
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rom_endian=OPTS.rom_endian,
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scramble_bits=OPTS.scramble_bits,
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strap_spacing=OPTS.strap_spacing,
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data_type=OPTS.data_type)
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if name is None:
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name = OPTS.output_name
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rom_config.set_local_config(self)
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# reset the static duplicate name checker for unit tests
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# in case we create more than one ROM
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from openram.base import design
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design.name_map=[]
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debug.print_raw("create rom of word size {0} with {1} num of words".format(self.word_size,
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self.num_words))
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start_time = datetime.datetime.now()
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self.name = name
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import openram.modules.rom_bank as rom
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self.r = rom(name, rom_config)
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self.r.create_netlist()
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if not OPTS.netlist_only:
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self.r.create_layout()
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if not OPTS.is_unit_test:
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print_time("ROM creation", datetime.datetime.now(), start_time)
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def sp_write(self, name, lvs=False, trim=False):
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self.r.sp_write(name, lvs, trim)
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def lef_write(self, name):
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self.r.lef_write(name)
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def gds_write(self, name):
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self.r.gds_write(name)
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def verilog_write(self, name):
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self.r.verilog_write(name)
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def extended_config_write(self, name):
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"""Dump config file with all options.
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Include defaults and anything changed by input config."""
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f = open(name, "w")
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var_dict = dict((name, getattr(OPTS, name)) for name in dir(OPTS) if not name.startswith('__') and not callable(getattr(OPTS, name)))
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for var_name, var_value in var_dict.items():
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if isinstance(var_value, str):
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f.write(str(var_name) + " = " + "\"" + str(var_value) + "\"\n")
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else:
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f.write(str(var_name) + " = " + str(var_value)+ "\n")
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f.close()
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def save(self):
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""" Save all the output files while reporting time to do it as well. """
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# Import this at the last minute so that the proper tech file
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# is loaded and the right tools are selected
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from openram import verify
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# Save the spice file
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start_time = datetime.datetime.now()
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spname = OPTS.output_path + self.r.name + ".sp"
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debug.print_raw("SP: Writing to {0}".format(spname))
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self.sp_write(spname)
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print_time("Spice writing", datetime.datetime.now(), start_time)
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if not OPTS.netlist_only:
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# Write the layout
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start_time = datetime.datetime.now()
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gdsname = OPTS.output_path + self.r.name + ".gds"
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debug.print_raw("GDS: Writing to {0}".format(gdsname))
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self.gds_write(gdsname)
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if OPTS.check_lvsdrc:
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verify.write_drc_script(cell_name=self.r.name,
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gds_name=os.path.basename(gdsname),
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extract=True,
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final_verification=True,
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output_path=OPTS.output_path)
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print_time("GDS", datetime.datetime.now(), start_time)
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# Create a LEF physical model
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start_time = datetime.datetime.now()
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lefname = OPTS.output_path + self.r.name + ".lef"
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debug.print_raw("LEF: Writing to {0}".format(lefname))
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self.lef_write(lefname)
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print_time("LEF", datetime.datetime.now(), start_time)
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# Save the LVS file
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start_time = datetime.datetime.now()
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lvsname = OPTS.output_path + self.r.name + ".lvs.sp"
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debug.print_raw("LVS: Writing to {0}".format(lvsname))
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self.sp_write(lvsname, lvs=True)
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if not OPTS.netlist_only and OPTS.check_lvsdrc:
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verify.write_lvs_script(cell_name=self.r.name,
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gds_name=os.path.basename(gdsname),
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sp_name=os.path.basename(lvsname),
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final_verification=True,
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output_path=OPTS.output_path)
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print_time("LVS writing", datetime.datetime.now(), start_time)
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# Save the extracted spice file
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if OPTS.use_pex:
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start_time = datetime.datetime.now()
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# Output the extracted design if requested
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pexname = OPTS.output_path + self.r.name + ".pex.sp"
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spname = OPTS.output_path + self.r.name + ".sp"
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verify.run_pex(self.r.name, gdsname, spname, output=pexname)
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sp_file = pexname
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print_time("Extraction", datetime.datetime.now(), start_time)
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else:
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# Use generated spice file for characterization
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sp_file = spname
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# Save a functional simulation file
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# TODO: Characterize the design
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# Write the config file
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# Should also save the provided data file
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start_time = datetime.datetime.now()
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from shutil import copyfile
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copyfile(OPTS.config_file, OPTS.output_path + OPTS.output_name + '.py')
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os.makedirs(os.path.dirname(OPTS.output_path + self.rom_data), exist_ok=True)
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copyfile(self.rom_data, OPTS.output_path + self.rom_data)
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debug.print_raw("Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py'))
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print_time("Config", datetime.datetime.now(), start_time)
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# TODO: Write the datasheet
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#Write a verilog model
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start_time = datetime.datetime.now()
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vname = OPTS.output_path + self.r.name + '.v'
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debug.print_raw("Verilog: Writing to {0}".format(vname))
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self.verilog_write(vname)
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print_time("Verilog", datetime.datetime.now(), start_time)
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# Write out options if specified
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if OPTS.output_extended_config:
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start_time = datetime.datetime.now()
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oname = OPTS.output_path + OPTS.output_name + "_extended.py"
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debug.print_raw("Extended Config: Writing to {0}".format(oname))
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self.extended_config_write(oname)
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print_time("Extended Config", datetime.datetime.now(), start_time)
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