mirror of https://github.com/VLSIDA/OpenRAM.git
239 lines
7.7 KiB
Python
239 lines
7.7 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import os
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import optparse
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class options(optparse.Values):
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"""
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Class for holding all of the OpenRAM options. All
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of these options can be over-riden in a configuration file
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that is the sole required command-line positional argument for sram_compiler.py.
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"""
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###################
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# Configuration options
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###################
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# This is the technology directory.
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openram_tech = ""
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# This is the name of the technology.
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tech_name = ""
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# Port configuration (1-2 ports allowed)
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num_rw_ports = 1
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num_r_ports = 0
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num_w_ports = 0
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# By default, don't use hierarchical wordline
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local_array_size = 0
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# Write mask size, default will be overwritten with word_size if not user specified
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write_size = None
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# These will get initialized by the user or the tech file
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nominal_corner_only = False
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supply_voltages = ""
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temperatures = ""
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process_corners = ""
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load_scales = ""
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slew_scales = ""
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# Size parameters must be specified by user in config file.
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# num_words = 0
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# word_size = 0
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# You can manually specify banks, but it is better to auto-detect it.
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num_banks = 1
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words_per_row = None
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num_spare_rows = 0
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num_spare_cols = 0
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###################
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# ROM configuration options
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###################
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rom_endian = "little"
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rom_data = None
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data_type = "bin"
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strap_spacing = 8
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scramble_bits = True
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###################
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# Control logic options
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###################
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# Approximate percentage of delay compared to bitlines
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rbl_delay_percentage = 0.5
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# FIXME: delay_control_scaling_factor is not used because
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# the multi-delay chain is not being sized automatically
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# if delay chain is automatically sized in delay based control logic
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# this multiplier can be used to add a guard band to the standard timing
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# lowering it can improve performance but may cause sram to fail
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# delay_control_scaling_factor = 1.0
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# multi delay chain is NOT automatically sized, needs to be set by user
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# list indexes 0 & 1 need to be even for polarity
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# list indexes 2 - 4 need to be odd for polarity
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# these default values are the ones used on the September 2023 Chipignite Shuttle
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# to test delay based control logic with sky130 1rw1r 8x1024 bit (1KB) with 8 column mux
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multi_delay_chain_pinouts = [2, 10, 11, 17, 31]
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# stages for delay chain in rbl control logic only
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delay_chain_stages = 9
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# fanout per stage for any control logic
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delay_chain_fanout_per_stage = 4
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accuracy_requirement = 0.75
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###################
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# Debug options.
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###################
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# This is the temp directory where all intermediate results are stored.
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try:
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# If user defined the temporary location in their environment, use it
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openram_temp = os.path.abspath(os.environ.get("OPENRAM_TMP"))
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except:
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openram_temp = "/tmp"
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# This is the verbosity level to control debug information. 0 is none, 1
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# is minimal, etc.
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verbose_level = 0
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# Drop to pdb on failure?
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debug = False
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# Only use corners in config file. Disables generated corners
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only_use_config_corners = False
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# A list of PVT tuples and be given and only these will be characterized
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use_specified_corners = None
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# Allows specification of model data
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sim_data_path = None
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# A list of load/slew tuples
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use_specified_load_slew = None
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# Spice simulation raw file
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spice_raw_file = None
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###################
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# Run-time vs accuracy options.
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# Default, sacrifice accuracy/completeness for speed.
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# Must turn on options for verification, final routing, etc.
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###################
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# When enabled, layout is not generated (and no DRC or LVS are performed)
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netlist_only = False
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# Whether we should do the final power routing
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route_supplies = True
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supply_pin_type = "ring"
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# This determines whether LVS and DRC is checked at all.
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check_lvsdrc = False
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# This determines whether LVS and DRC is checked for every submodule.
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inline_lvsdrc = False
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# Remove noncritical memory cells for characterization speed-up
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trim_netlist = True
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# Run with extracted parasitics
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use_pex = False
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# Output config with all options
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output_extended_config = False
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# Output temporary file used to format HTML page
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output_datasheet_info = True
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# Determines which analytical model to use.
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# Available Models: elmore, linear_regression
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model_name = "elmore"
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# Write graph to a file
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write_graph = False
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###################
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# Tool options
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###################
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# Top process that was ran (openram, memchar, memfunc)
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top_process = None
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# Use conda to install the default tools
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# (existing tools will be used if disabled)
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use_conda = True
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# Variable to select the variant of spice
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spice_name = None
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# The spice executable being used which is derived from the user PATH.
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spice_exe = None
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# Variable to select the variant of drc, lvs, pex
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drc_name = None
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lvs_name = None
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pex_name = None
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# The DRC/LVS/PEX executable being used
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# which is derived from the user PATH.
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drc_exe = None
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lvs_exe = None
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pex_exe = None
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# For sky130, we need magic for filtering.
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magic_exe = None
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# Number of threads to use
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num_threads = 1
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# Number of threads to use in ngspice/hspice
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num_sim_threads = 3
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# Some tools (e.g. Xyce) use other separators like ":"
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hier_seperator = "."
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# Should we print out the banner at startup
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print_banner = True
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# Define the output file paths
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output_path = "."
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# Define the output file base name
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output_name = ""
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# Use analytical delay models by default
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# rather than (slow) characterization
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analytical_delay = True
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# Purge the temp directory after a successful
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# run (doesn't purge on errors, anyhow)
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# Bitline, s_en and cell names used in characterizer
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bl_format = "X{name}{hier_sep}xbank0{hier_sep}bl_{row}_{col}"
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br_format = "X{name}{hier_sep}xbank0{hier_sep}br_{row}_{col}"
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sen_format = "X{name}{hier_sep}xbank0{hier_sep}s_en"
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cell_format = "X{name}{hier_sep}xbank0{hier_sep}xbitcell_array{hier_sep}xreplica_bitcell_array{hier_sep}xbitcell_array{hier_sep}xbit_r{row}_c{col}"
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# Random seed for functional simulation
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functional_seed = None
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# Route the input/output pins to the perimeter
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perimeter_pins = True
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# Detailed or abstract LEF view
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detailed_lef = False
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keep_temp = False
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# These are the default modules that can be over-riden
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bank_select = "bank_select"
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bitcell_array = "bitcell_array"
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bitcell = "bitcell"
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buf_dec = "pbuf"
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column_decoder = "column_decoder"
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column_mux_array = "column_mux_array"
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control_logic = "control_logic"
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decoder = "hierarchical_decoder"
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delay_chain = "delay_chain"
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dff_array = "dff_array"
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dff = "dff"
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inv_dec = "pinv"
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nand2_dec = "pnand2"
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nand3_dec = "pnand3"
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nand4_dec = "pnand4" # Not available right now
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precharge = "precharge"
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precharge_array = "precharge_array"
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ptx = "ptx"
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replica_bitline = "replica_bitline"
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sense_amp_array = "sense_amp_array"
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sense_amp = "sense_amp"
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tri_gate_array = "tri_gate_array"
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tri_gate = "tri_gate"
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wordline_driver = "wordline_driver"
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write_driver_array = "write_driver_array"
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write_driver = "write_driver"
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write_mask_and_array = "write_mask_and_array"
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