OpenRAM/compiler/bitcells
mrg aa8f389f28 Add fudge factor to pbitcell wells 2020-01-24 17:45:24 +00:00
..
bitcell.py Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
bitcell_1rw_1r.py Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
bitcell_1w_1r.py Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
bitcell_base.py Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
dummy_bitcell.py Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
dummy_bitcell_1rw_1r.py Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
dummy_bitcell_1w_1r.py Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
dummy_pbitcell.py Add bbox for special DRC rule boundary 2019-12-05 23:14:25 +00:00
pbitcell.py Add fudge factor to pbitcell wells 2020-01-24 17:45:24 +00:00
replica_bitcell.py Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
replica_bitcell_1rw_1r.py Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
replica_bitcell_1w_1r.py Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
replica_pbitcell.py Add bbox for special DRC rule boundary 2019-12-05 23:14:25 +00:00