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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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e5dcf5d5b1340b43376ef93b339015f33df5b785
OpenRAM/technology/freepdk45/sp_lib
T
History
Hunter Nichols 4f08062268 Added custom 1rw+1r bitcell. Testing are currently failing.
2018-10-22 17:02:21 -07:00
..
cell_1rw_1r.sp
Added custom 1rw+1r bitcell. Testing are currently failing.
2018-10-22 17:02:21 -07:00
cell_6t.sp
Change internal nets of 6T cell and write driver to have useful names for debugging.
2018-07-26 11:26:47 -07:00
dff.sp
Add dff_buf for buffered flop arrays.
2018-03-04 16:13:10 -08:00
replica_cell_6t.sp
RELEASE 1.0
2016-11-08 09:57:35 -08:00
sense_amp.sp
Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder.
2018-02-02 14:08:56 -08:00
tri_gate.sp
RELEASE 1.0
2016-11-08 09:57:35 -08:00
write_driver.sp
Change wen to en in spice lib files. Check lvs report insted of stdout with netgen.
2018-02-01 05:38:48 -08:00
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