Matt Guthaus ce8c2d983d Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

..

bank_select.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

bank.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

bitcell_array.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

control_logic.py

Converted all submodules to use _bit notation instead of [bit]

2018-10-11 09:53:08 -07:00

delay_chain.py

Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port.

2018-09-26 19:10:24 -07:00

dff_array.py

Merge branch 'multiport' into supply_routing

2018-10-11 09:56:38 -07:00

dff_buf_array.py

Merge branch 'multiport' into supply_routing

2018-10-11 09:56:38 -07:00

dff_buf.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

dff_inv_array.py

Merge branch 'multiport' into supply_routing

2018-10-11 09:56:38 -07:00

dff_inv.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

dff.py

Remove ms_flop and replace with dff. Might break setup_hold tests.

2018-09-13 11:02:28 -07:00

hierarchical_decoder.py

Converted all submodules to use _bit notation instead of [bit]

2018-10-11 09:53:08 -07:00

hierarchical_predecode2x4.py

Converted all submodules to use _bit notation instead of [bit]

2018-10-11 09:53:08 -07:00

hierarchical_predecode3x8.py

Converted all submodules to use _bit notation instead of [bit]

2018-10-11 09:53:08 -07:00

hierarchical_predecode.py

Merge branch 'multiport' into supply_routing

2018-10-11 09:56:38 -07:00

multibank.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

precharge_array.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

replica_bitcell.py

Finish renaming replica bitcell and bitline pin names.

2018-09-04 14:03:15 -07:00

replica_bitline.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

replica_pbitcell.py

Correcting format of replica_pbitcell.

2018-09-13 18:51:52 -07:00

sense_amp_array.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

sense_amp.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

single_level_column_mux_array.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

tri_gate_array.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

tri_gate.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

wordline_driver.py

Converted all submodules to use _bit notation instead of [bit]

2018-10-11 09:53:08 -07:00

write_driver_array.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

write_driver.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00