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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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e28978180fa931b45e0c9bf3ea599f996a51ddb5
OpenRAM/compiler/bitcells
T
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Matt Guthaus ef2ed9a92c Simplify bl and br name lists.
2018-11-08 15:48:49 -08:00
..
bitcell_1rw_1r.py
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
bitcell.py
Simplify bl and br name lists.
2018-11-08 15:48:49 -08:00
pbitcell.py
Simplify bl and br name lists.
2018-11-08 15:48:49 -08:00
replica_bitcell_1rw_1r.py
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
replica_bitcell.py
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
replica_pbitcell.py
Move replica bitcells to new bitcells subdir
2018-10-24 09:06:29 -07:00
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