mirror of https://github.com/VLSIDA/OpenRAM.git
471 lines
22 KiB
Python
471 lines
22 KiB
Python
import sys,re,shutil
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from design import design
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import debug
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import math
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import tech
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import random
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from .stimuli import *
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from .charutils import *
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import utils
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from globals import OPTS
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from .simulation import simulation
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class functional(simulation):
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"""
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Functions to write random data values to a random address then read them back and check
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for successful SRAM operation.
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"""
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def __init__(self, sram, spfile, corner):
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super().__init__(sram, spfile, corner)
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self.set_corner(corner)
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self.set_spice_constants()
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self.set_stimulus_variables()
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# Number of checks can be changed
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self.num_checks = 1
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self.cycles = 0
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self.eo_period = []
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# set to 1 if functional simulation fails during any check
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self.functional_fail = 0
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self.error = ""
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def run(self):
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""" Main function to generate random writes/reads, run spice, and analyze results """
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self.noop()
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self.overwrite_test()
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self.write_read_test()
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self.noop()
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# Run SPICE simulation
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self.write_functional_stimulus()
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self.stim.run_sim()
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# Extrat DOUT values from spice timing.lis
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for i in range(2*self.num_checks):
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self.sp_read_value = ["" for port in range(self.total_read)]
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for port in range(self.total_read):
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for bit in range(self.word_size):
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value = parse_spice_list("timing", "vdout{0}.{1}.ck{2}".format(self.read_index[port],bit,i))
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if value > 0.9 * self.vdd_voltage:
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self.sp_read_value[port] = "1" + self.sp_read_value[port]
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elif value < 0.1 * self.vdd_voltage:
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self.sp_read_value[port] = "0" + self.sp_read_value[port]
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else:
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self.functional_fail = 1
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self.error ="FAILED: DOUT{0}[{1}] value {2} at time {3}n does not fall within noise margins <{4} or >{5}.".format(port,
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bit,
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value,
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self.eo_period[i],
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0.1*self.vdd_voltage,
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0.9*self.vdd_voltage)
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if self.functional_fail:
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return (self.functional_fail, self.error)
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if i < self.num_checks:
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self.read_values_over_test[i].append(self.sp_read_value[port])
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else:
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self.read_values_test[i-self.num_checks].append(self.sp_read_value[port])
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# Compare written values to read values
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for i in range(self.num_checks):
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debug.info(1, "Stored Word - Overwrite Test: {}".format(self.stored_values_over_test[i]))
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debug.info(1, "Read Word - Overwrite Test: {}".format(self.read_values_over_test[i]))
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for port in range(self.total_read):
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if self.stored_values_over_test[i] != self.read_values_over_test[i][port]:
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self.functional_fail = 1
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self.error ="FAILED: Overwrite Test - read value {0} does not match writen value {1}.".format(self.read_values_over_test[i][port],
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self.stored_values_over_test[i])
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for i in range(self.num_checks):
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debug.info(1, "Stored Word - Standard W/R Test: {}".format(self.stored_values_test[i]))
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debug.info(1, "Read Word - Standard W/R Test: {}".format(self.read_values_test[i]))
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for port in range(self.total_read):
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if self.stored_values_test[i] != self.read_values_test[i][port]:
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self.functional_fail = 1
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self.error ="FAILED: Standard W/R Test - read value {0} does not match writen value {1}.".format(self.read_values_test[i][port],
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self.stored_values_test[i])
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return (self.functional_fail, self.error)
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def multiport_run(self):
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""" Main function to generate random writes/reads, run spice, and analyze results. This function includes a multiport check. """
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self.noop()
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self.multi_read_test()
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self.overwrite_test()
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self.write_read_test()
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self.noop()
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# Run SPICE simulation
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self.write_functional_stimulus()
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self.stim.run_sim()
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# Extrat DOUT values from spice timing.lis
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for i in range(3*self.num_checks):
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self.sp_read_value = ["" for port in range(self.total_read)]
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for port in range(self.total_read):
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for bit in range(self.word_size):
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value = parse_spice_list("timing", "vdout{0}.{1}.ck{2}".format(self.read_index[port],bit,i))
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if value > 0.9 * self.vdd_voltage:
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self.sp_read_value[port] = "1" + self.sp_read_value[port]
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elif value < 0.1 * self.vdd_voltage:
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self.sp_read_value[port] = "0" + self.sp_read_value[port]
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else:
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self.functional_fail = 1
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self.error ="FAILED: DOUT{0}[{1}] value {2} at time {3}n does not fall within noise margins <{4} or >{5}.".format(port,
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bit,
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value,
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self.eo_period[i],
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0.1*self.vdd_voltage,
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0.9*self.vdd_voltage)
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if self.functional_fail:
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return (self.functional_fail, self.error)
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if i < self.num_checks:
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self.read_values_multi_test[i][self.multi_addrs[i][port]] = self.sp_read_value[port]
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elif i < 2*self.num_checks:
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self.read_values_over_test[i-self.num_checks].append(self.sp_read_value[port])
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else:
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self.read_values_test[i-2*self.num_checks].append(self.sp_read_value[port])
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# Compare written values to read values
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for i in range(self.num_checks):
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debug.info(1, "Stored Words - Multi Test (addr:word): {}".format(self.stored_values_multi_test[i]))
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debug.info(1, "Read Words - Mutlti Test (addr:word): {}".format(self.read_values_multi_test[i]))
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for addr in self.multi_addrs[i]:
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if self.stored_values_multi_test[i][addr] != self.read_values_multi_test[i][addr]:
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self.functional_fail = 1
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self.error ="FAILED: Multi Test - read value {0} does not match writen value {1}.".format(self.read_values_multi_test[i][addr],
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self.stored_values_multi_test[i][addr])
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for i in range(self.num_checks):
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debug.info(1, "Stored Word - Overwrite Test: {}".format(self.stored_values_over_test[i]))
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debug.info(1, "Read Word - Overwrite Test: {}".format(self.read_values_over_test[i]))
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for port in range(self.total_read):
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if self.stored_values_over_test[i] != self.read_values_over_test[i][port]:
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self.functional_fail = 1
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self.error ="FAILED: Overwrite Test - read value {0} does not match writen value {1}.".format(self.read_values_over_test[i][port],
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self.stored_values_over_test[i])
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for i in range(self.num_checks):
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debug.info(1, "Stored Word - Standard W/R Test: {}".format(self.stored_values_test[i]))
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debug.info(1, "Read Word - Standard W/R Test: {}".format(self.read_values_test[i]))
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for port in range(self.total_read):
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if self.stored_values_test[i] != self.read_values_test[i][port]:
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self.functional_fail = 1
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self.error ="FAILED: Standard W/R Test - read value {0} does not match writen value {1}.".format(self.read_values_test[i][port],
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self.stored_values_test[i])
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return (self.functional_fail, self.error)
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def multi_read_test(self):
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""" Multiport functional test to see if mutliple words on multiple addresses can be accessed at the same time. """
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self.stored_values_multi_test = [{} for i in range(self.num_checks)]
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self.read_values_multi_test = [{} for i in range(self.num_checks)]
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self.multi_addrs = []
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for i in range(self.num_checks):
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# Write random words to a random addresses until there are as many stored words as there are RW and R ports
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while(len(self.stored_values_multi_test[i]) < self.total_read):
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addr = self.gen_addr()
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word = self.gen_data()
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self.write(addr,word)
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self.stored_values_multi_test[i][addr] = word
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# Each RW and R port will read from a different address
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stored_addrs = []
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stored_words = []
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for (addr,word) in self.stored_values_multi_test[i].items():
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stored_addrs.append(addr)
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stored_words.append(word)
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self.multi_addrs.append(stored_addrs)
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self.multi_read(stored_addrs,stored_words)
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def overwrite_test(self):
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""" Functional test to see if a word at a particular address can be overwritten without being corrupted. """
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self.stored_values_over_test = []
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self.read_values_over_test = [[] for i in range(self.num_checks)]
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for i in range(self.num_checks):
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# Write a random word to a random address 3 different times, overwriting the stored word twice
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addr = self.gen_addr()
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for j in range(2):
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word = self.gen_data()
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self.write(addr,word)
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self.stored_values_over_test.append(word)
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# Read word from address (use all RW and R ports)
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self.read(addr,word)
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def write_read_test(self):
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""" A standard functional test for writing to an address and reading back the value. """
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self.stored_values_test = []
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self.read_values_test = [[] for i in range(self.num_checks)]
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for i in range(self.num_checks):
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# Write a random word to a random address
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addr = self.gen_addr()
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word = self.gen_data()
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self.write(addr,word)
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self.stored_values_test.append(word)
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# Read word from address (use all RW and R ports)
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self.read(addr,word)
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def noop(self):
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""" Noop cycle. """
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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for port in range(self.total_ports):
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self.csb_values[port].append(1)
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for port in range(self.total_write):
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self.web_values[port].append(1)
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for port in range(self.total_ports):
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for bit in range(self.addr_size):
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self.addr_values[port][bit].append(0)
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for port in range(self.total_write):
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for bit in range(self.word_size):
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self.data_values[port][bit].append(0)
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def write(self,addr,word,write_port=0):
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""" Generates signals for a write cycle. """
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debug.info(1, "Writing {0} to address {1} in cycle {2}...".format(word,addr,self.cycles))
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self.cycles += 1
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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# Write control signals
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for port in range(self.total_ports):
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if port == write_port:
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self.csb_values[port].append(0)
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else:
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self.csb_values[port].append(1)
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for port in range(self.total_write):
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if port == write_port:
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self.web_values[port].append(0)
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else:
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self.web_values[port].append(1)
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# Write address
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for port in range(self.total_ports):
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for bit in range(self.addr_size):
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current_address_bit = int(addr[self.addr_size-1-bit])
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self.addr_values[port][bit].append(current_address_bit)
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# Write data
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for port in range(self.total_write):
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for bit in range(self.word_size):
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current_word_bit = int(word[self.word_size-1-bit])
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self.data_values[port][bit].append(current_word_bit)
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def read(self,addr,word):
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""" Generates signals for a read cycle. """
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debug.info(1, "Reading {0} from address {1} in cycle {2}...".format(word,addr,self.cycles))
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self.cycles += 1
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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# Read control signals
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for port in range(self.total_ports):
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if self.port_id[port] == "w":
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self.csb_values[port].append(1)
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else:
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self.csb_values[port].append(0)
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for port in range(self.total_write):
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self.web_values[port].append(1)
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# Read address
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for port in range(self.total_ports):
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for bit in range(self.addr_size):
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current_address_bit = int(addr[self.addr_size-1-bit])
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self.addr_values[port][bit].append(current_address_bit)
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# Data input doesn't matter during read cycle, so arbitrarily set to 0 for simulation
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for port in range(self.total_write):
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for bit in range(self.word_size):
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self.data_values[port][bit].append(0)
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# Record the end of the period that the read operation occured in
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self.eo_period.append(self.t_current)
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def multi_read(self,addrs,words):
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""" Generates signals for a read cycle but all ports read from a different address. The inputs 'addrs' and 'words' are lists. """
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debug.info(1, "Reading {0} from addresses {1} in cycle {2}...".format(words,addrs,self.cycles))
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self.cycles += 1
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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# Read control signals
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for port in range(self.total_ports):
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if self.port_id[port] == "w":
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self.csb_values[port].append(1)
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else:
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self.csb_values[port].append(0)
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for port in range(self.total_write):
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self.web_values[port].append(1)
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# Read address
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addr_index = 0
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for port in range(self.total_ports):
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for bit in range(self.addr_size):
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if self.port_id[port] == "w":
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current_address_bit = 0
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else:
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current_address_bit = int(addrs[addr_index][self.addr_size-1-bit])
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self.addr_values[port][bit].append(current_address_bit)
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if self.port_id[port] != "w":
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addr_index += 1
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# Data input doesn't matter during read cycle, so arbitrarily set to 0 for simulation
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for port in range(self.total_write):
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for bit in range(self.word_size):
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self.data_values[port][bit].append(0)
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# Record the end of the period that the read operation occured in
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self.eo_period.append(self.t_current)
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def gen_data(self):
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""" Generates a random word to write. """
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rand = random.randint(0,(2**self.word_size)-1)
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data_bits = self.convert_to_bin(rand,False)
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return data_bits
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def gen_addr(self):
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""" Generates a random address value to write to. """
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rand = random.randint(0,(2**self.addr_size)-1)
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addr_bits = self.convert_to_bin(rand,True)
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return addr_bits
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def get_data(self):
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""" Gets an available address and corresponding word. """
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# Currently unused but may need later depending on how the functional test develops
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addr = random.choice(self.stored_words.keys())
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word = self.stored_words[addr]
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return (addr,word)
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def convert_to_bin(self,value,is_addr):
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""" Converts addr & word to usable binary values. """
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new_value = str.replace(bin(value),"0b","")
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if(is_addr):
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expected_value = self.addr_size
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else:
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expected_value = self.word_size
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for i in range (expected_value - len(new_value)):
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new_value = "0" + new_value
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#print("Binary Conversion: {} to {}".format(value, new_value))
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return new_value
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def obtain_cycle_times(self,period):
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""" Generate clock cycle times based on period and number of cycles. """
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t_current = 0
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self.cycle_times = []
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for i in range(self.cycles):
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self.cycle_times.append(t_current)
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t_current += period
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def write_functional_stimulus(self):
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""" Writes SPICE stimulus. """
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#self.obtain_cycle_times(self.period)
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temp_stim = "{0}/stim.sp".format(OPTS.openram_temp)
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self.sf = open(temp_stim,"w")
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self.sf.write("* Functional test stimulus file for {}ns period\n\n".format(self.period))
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self.stim = stimuli(self.sf,self.corner)
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#Write include statements
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self.sram_sp_file = "{}sram.sp".format(OPTS.openram_temp)
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shutil.copy(self.sp_file, self.sram_sp_file)
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self.stim.write_include(self.sram_sp_file)
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#Write Vdd/Gnd statements
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self.sf.write("\n* Global Power Supplies\n")
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self.stim.write_supply()
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#Instantiate the SRAM
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self.sf.write("\n* Instantiation of the SRAM\n")
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self.stim.inst_full_sram(sram=self.sram,
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sram_name=self.name)
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#self.stim.inst_sram(abits=self.addr_size,
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# dbits=self.word_size,
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# port_info=(self.total_ports,self.total_write,self.read_index,self.write_index),
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# sram_name=self.name)
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# Add load capacitance to each of the read ports
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self.sf.write("\n* SRAM output loads\n")
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for port in range(self.total_read):
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for bit in range(self.word_size):
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self.sf.write("CD{0}{1} DOUT{0}[{1}] 0 {2}f\n".format(self.read_index[port], bit, self.load))
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# Generate data input bits
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self.sf.write("\n* Generation of data and address signals\n")
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for port in range(self.total_write):
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for bit in range(self.word_size):
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sig_name = "DIN{0}[{1}]".format(port,bit)
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self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[port][bit], self.period, self.slew, 0.05)
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# Generate address bits
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for port in range(self.total_ports):
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for bit in range(self.addr_size):
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sig_name = "ADDR{0}[{1}]".format(port,bit)
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self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[port][bit], self.period, self.slew, 0.05)
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# Generate control signals
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self.sf.write("\n * Generation of control signals\n")
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for port in range(self.total_ports):
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self.stim.gen_pwl("CSB{}".format(port), self.cycle_times , self.csb_values[port], self.period, self.slew, 0.05)
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for port in range(self.total_write):
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|
self.stim.gen_pwl("WEB{}".format(port), self.cycle_times , self.web_values[port], self.period, self.slew, 0.05)
|
|
|
|
# Generate CLK signals
|
|
for port in range(self.total_ports):
|
|
self.stim.gen_pulse(sig_name="CLK{}".format(port),
|
|
v1=self.gnd_voltage,
|
|
v2=self.vdd_voltage,
|
|
offset=self.period,
|
|
period=self.period,
|
|
t_rise=self.slew,
|
|
t_fall=self.slew)
|
|
|
|
# Generate DOUT value measurements
|
|
if self.total_ports > 1:
|
|
num_tests = 3
|
|
else:
|
|
num_tests = 2
|
|
|
|
self.sf.write("\n * Generation of dout measurements\n")
|
|
for i in range(num_tests*self.num_checks):
|
|
t_intital = self.eo_period[i] - 0.01*self.period
|
|
t_final = self.eo_period[i] + 0.01*self.period
|
|
for port in range(self.total_read):
|
|
for bit in range(self.word_size):
|
|
self.stim.gen_meas_value(meas_name="VDOUT{0}[{1}]ck{2}".format(self.read_index[port],bit,i),
|
|
dout="DOUT{0}[{1}]".format(self.read_index[port],bit),
|
|
t_intital=t_intital,
|
|
t_final=t_final)
|
|
|
|
self.stim.write_control(self.cycle_times[-1] + self.period)
|
|
self.sf.close()
|
|
|
|
|