Jesse Cirimelli-Low e23289d5ae merge in dev

2023-08-10 17:04:45 -07:00

..

__init__.py

Verilog ROM model created for testing

2023-06-12 15:35:54 -07:00

channel_route.py

Update copyright year

2023-01-28 22:56:27 -08:00

contact.py

remove pins overwrite from contact class

2023-07-18 16:12:42 -07:00

delay_data.py

Update copyright year

2023-01-28 22:56:27 -08:00

design.py

Merge branch 'char' into STA-refactor

2023-07-19 12:35:22 -07:00

errors.py

Update copyright year

2023-01-28 22:56:27 -08:00

geometry.py

merge in dev

2023-08-10 17:04:45 -07:00

hierarchy_design.py

get connections from spice objects in instances

2023-07-18 10:50:50 -07:00

hierarchy_layout.py

merge in dev

2023-08-10 17:04:45 -07:00

hierarchy_spice.py

cleanup net_spice docstrings

2023-07-19 12:45:41 -07:00

lef.py

implement pin_spice object

2023-07-13 16:45:05 -07:00

logical_effort.py

Update copyright year

2023-01-28 22:56:27 -08:00

pin_layout.py

Update copyright year

2023-01-28 22:56:27 -08:00

power_data.py

Update copyright year

2023-01-28 22:56:27 -08:00

rom_verilog.py

Fixed formatting on all files

2023-06-14 12:28:36 -07:00

route.py

Update copyright year

2023-01-28 22:56:27 -08:00

timing_graph.py

Update copyright year

2023-01-28 22:56:27 -08:00

utils.py

Update copyright year

2023-01-28 22:56:27 -08:00

vector3d.py

Update copyright year

2023-01-28 22:56:27 -08:00

vector.py

Update copyright year

2023-01-28 22:56:27 -08:00

verilog.py

Update copyright year

2023-01-28 22:56:27 -08:00

wire_path.py

Update copyright year

2023-01-28 22:56:27 -08:00

wire_spice_model.py

add fixme note for unit conversion

2023-06-28 14:05:42 -07:00

wire.py

Update copyright year

2023-01-28 22:56:27 -08:00