mirror of https://github.com/VLSIDA/OpenRAM.git
229 lines
8.8 KiB
Python
229 lines
8.8 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California
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# All rights reserved.
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#
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import debug
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import design
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from tech import cell_properties
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from sram_factory import factory
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from vector import vector
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from globals import OPTS
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class replica_column(design.design):
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"""
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Generate a replica bitline column for the replica array.
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Rows is the total number of rows i the main array.
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rbl is a tuple with the number of left and right replica bitlines.
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Replica bit specifies which replica column this is (to determine where to put the
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replica cell relative to the bottom (including the dummy bit at 0).
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"""
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def __init__(self, name, rows, rbl, replica_bit, column_offset=0):
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super().__init__(name)
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self.rows = rows
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self.left_rbl = rbl[0]
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self.right_rbl = rbl[1]
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self.replica_bit = replica_bit
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# left, right, regular rows plus top/bottom dummy cells
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self.total_size = self.left_rbl + rows + self.right_rbl + 2
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self.column_offset = column_offset
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debug.check(replica_bit != 0 and replica_bit != rows,
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"Replica bit cannot be the dummy row.")
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debug.check(replica_bit <= self.left_rbl or replica_bit >= self.total_size - self.right_rbl - 1,
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"Replica bit cannot be in the regular array.")
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if OPTS.tech_name == "sky130":
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debug.check(rows % 2 == 0 and (self.left_rbl + 1) % 2 == 0,
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"sky130 currently requires rows to be even and to start with X mirroring"
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+ " (left_rbl must be odd) for LVS.")
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.height = self.total_size * self.cell.height
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self.width = self.cell.width
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self.place_instances()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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for bl_name in self.cell.get_all_bitline_names():
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# In the replica column, these are only outputs!
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self.add_pin("{0}_{1}".format(bl_name, 0), "OUTPUT")
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for row in range(self.total_size):
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for wl_name in self.cell.get_all_wl_names():
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self.add_pin("{0}_{1}".format(wl_name, row), "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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self.replica_cell = factory.create(module_type="replica_{}".format(OPTS.bitcell))
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self.add_mod(self.replica_cell)
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self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell))
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self.add_mod(self.dummy_cell)
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try:
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edge_module_type = ("col_cap" if cell_properties.bitcell.end_caps else "dummy")
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except AttributeError:
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edge_module_type = "dummy"
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self.edge_cell = factory.create(module_type=edge_module_type + "_" + OPTS.bitcell)
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self.add_mod(self.edge_cell)
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# Used for pin names only
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self.cell = factory.create(module_type="bitcell")
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def create_instances(self):
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try:
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end_caps_enabled = cell_properties.bitcell.end_caps
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except AttributeError:
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end_caps_enabled = False
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self.cell_inst = {}
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for row in range(self.total_size):
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name="rbc_{0}".format(row)
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# Top/bottom cell are always dummy cells.
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# Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
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# Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
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if (row > self.left_rbl and row < self.total_size - self.right_rbl - 1):
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self.cell_inst[row]=self.add_inst(name=name,
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mod=self.replica_cell)
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self.connect_inst(self.get_bitcell_pins(row, 0))
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elif row==self.replica_bit:
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self.cell_inst[row]=self.add_inst(name=name,
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mod=self.replica_cell)
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self.connect_inst(self.get_bitcell_pins(row, 0))
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elif (row == 0 or row == self.total_size - 1):
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self.cell_inst[row]=self.add_inst(name=name,
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mod=self.edge_cell)
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if end_caps_enabled:
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self.connect_inst(self.get_bitcell_pins_col_cap(row, 0))
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else:
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self.connect_inst(self.get_bitcell_pins(row, 0))
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else:
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self.cell_inst[row]=self.add_inst(name=name,
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mod=self.dummy_cell)
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self.connect_inst(self.get_bitcell_pins(row, 0))
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def place_instances(self):
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from tech import cell_properties
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# Flip the mirrors if we have an odd number of replica+dummy rows at the bottom
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# so that we will start with mirroring rather than not mirroring
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rbl_offset = (self.left_rbl + 1) %2
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# if our bitcells are mirrored on the y axis, check if we are in global
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# column that needs to be flipped.
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dir_y = False
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xoffset = 0
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if cell_properties.bitcell.mirror.y and self.column_offset % 2:
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dir_y = True
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xoffset = self.replica_cell.width
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for row in range(self.total_size):
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# name = "bit_r{0}_{1}".format(row, "rbl")
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dir_x = cell_properties.bitcell.mirror.x and (row + rbl_offset) % 2
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offset = vector(xoffset, self.cell.height * (row + (row + rbl_offset) % 2))
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if dir_x and dir_y:
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dir_key = "XY"
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elif dir_x:
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dir_key = "MX"
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elif dir_y:
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dir_key = "MY"
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else:
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dir_key = ""
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self.cell_inst[row].place(offset=offset,
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mirror=dir_key)
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def add_layout_pins(self):
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""" Add the layout pins """
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for bl_name in self.cell.get_all_bitline_names():
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bl_pin = self.cell_inst[0].get_pin(bl_name)
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self.add_layout_pin(text=bl_name,
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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try:
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end_caps_enabled = cell_properties.bitcell.end_caps
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except AttributeError:
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end_caps_enabled = False
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if end_caps_enabled:
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row_range_max = self.total_size - 1
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row_range_min = 1
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else:
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row_range_max = self.total_size
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row_range_min = 0
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for row in range(row_range_min, row_range_max):
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for wl_name in self.cell.get_all_wl_names():
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wl_pin = self.cell_inst[row].get_pin(wl_name)
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self.add_layout_pin(text="{0}_{1}".format(wl_name, row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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# Supplies are only connected in the ends
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for (index, inst) in self.cell_inst.items():
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for pin_name in ["vdd", "gnd"]:
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if inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]:
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self.copy_power_pins(inst, pin_name)
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else:
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self.copy_layout_pin(inst, pin_name)
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def get_bitcell_pins(self, row, col):
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""" Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array """
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bitcell_pins = []
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pin_names = self.cell.get_all_bitline_names()
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for pin in pin_names:
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bitcell_pins.append(pin + "_{0}".format(col))
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pin_names = self.cell.get_all_wl_names()
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for pin in pin_names:
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bitcell_pins.append(pin + "_{0}".format(row))
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bitcell_pins.append("vdd")
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bitcell_pins.append("gnd")
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return bitcell_pins
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def get_bitcell_pins_col_cap(self, row, col):
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""" Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array """
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bitcell_pins = []
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pin_names = self.cell.get_all_bitline_names()
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for pin in pin_names:
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bitcell_pins.append(pin + "_{0}".format(col))
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bitcell_pins.append("vdd")
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return bitcell_pins
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def exclude_all_but_replica(self):
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"""Excludes all bits except the replica cell (self.replica_bit)."""
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for row, cell in self.cell_inst.items():
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if row != self.replica_bit:
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self.graph_inst_exclude.add(cell)
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