mirror of https://github.com/VLSIDA/OpenRAM.git
161 lines
6.2 KiB
Python
161 lines
6.2 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram import debug
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from openram.base import vector
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from openram.sram_factory import factory
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from .pgate import *
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class pand3(pgate):
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"""
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This is a simple buffer used for driving loads.
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"""
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def __init__(self, name, size=1, height=None, vertical=False, add_wells=True):
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debug.info(1, "Creating pand3 {}".format(name))
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self.add_comment("size: {}".format(size))
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self.vertical = vertical
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self.size = size
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# Creates the netlist and layout
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super().__init__(name, height, add_wells)
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def create_netlist(self):
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self.add_pins()
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self.create_modules()
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self.create_insts()
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def create_modules(self):
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# Shield the cap, but have at least a stage effort of 4
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self.nand = factory.create(module_type="pnand3",
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height=self.height,
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add_wells=self.vertical)
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# Add the well tap to the inverter because when stacked
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# vertically it is sometimes narrower
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self.inv = factory.create(module_type="pdriver",
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size_list=[self.size],
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height=self.height,
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add_wells=self.add_wells)
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def create_layout(self):
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if self.vertical:
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self.height = 2 * self.nand.height
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self.width = max(self.nand.width, self.inv.width)
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else:
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self.width = self.nand.width + self.inv.width
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self.place_insts()
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self.add_wires()
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self.add_layout_pins()
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self.route_supply_rails()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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self.add_pin("A", "INPUT")
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self.add_pin("B", "INPUT")
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self.add_pin("C", "INPUT")
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self.add_pin("Z", "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_insts(self):
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self.nand_inst = self.add_inst(name="pand3_nand",
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mod=self.nand)
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self.connect_inst(["A", "B", "C", "zb_int", "vdd", "gnd"])
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self.inv_inst = self.add_inst(name="pand3_inv",
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mod=self.inv)
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self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
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def place_insts(self):
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# Add NAND to the right
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self.nand_inst.place(offset=vector(0, 0))
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if self.vertical:
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# Add INV above
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self.inv_inst.place(offset=vector(self.inv.width,
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2 * self.nand.height),
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mirror="XY")
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else:
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# Add INV to the right
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self.inv_inst.place(offset=vector(self.nand_inst.rx(), 0))
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def route_supply_rails(self):
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""" Add vdd/gnd rails to the top, (middle), and bottom. """
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self.add_layout_pin_rect_center(text="gnd",
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layer=self.route_layer,
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offset=vector(0.5 * self.width, 0),
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width=self.width)
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# Second gnd of the inverter gate
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if self.vertical:
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self.add_layout_pin_rect_center(text="gnd",
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layer=self.route_layer,
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offset=vector(0.5 * self.width, self.height),
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width=self.width)
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if self.vertical:
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# Shared between two gates
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y_offset = 0.5 * self.height
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else:
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y_offset = self.height
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self.add_layout_pin_rect_center(text="vdd",
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layer=self.route_layer,
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offset=vector(0.5 * self.width, y_offset),
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width=self.width)
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def add_wires(self):
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# nand Z to inv A
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z1_pin = self.nand_inst.get_pin("Z")
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a2_pin = self.inv_inst.get_pin("A")
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if self.vertical:
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route_layer = "m2"
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self.add_via_stack_center(offset=z1_pin.center(),
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from_layer=z1_pin.layer,
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to_layer=route_layer)
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self.add_zjog(route_layer,
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z1_pin.uc(),
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a2_pin.bc(),
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"V")
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self.add_via_stack_center(offset=a2_pin.center(),
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from_layer=a2_pin.layer,
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to_layer=route_layer)
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else:
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route_layer = self.route_layer
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mid1_point = vector(z1_pin.cx(), a2_pin.cy())
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self.add_path(route_layer,
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[z1_pin.center(), mid1_point, a2_pin.center()])
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def add_layout_pins(self):
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pin = self.inv_inst.get_pin("Z")
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self.add_layout_pin_rect_center(text="Z",
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layer=pin.layer,
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offset=pin.center(),
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width=pin.width(),
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height=pin.height())
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for pin_name in ["A", "B", "C"]:
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pin = self.nand_inst.get_pin(pin_name)
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self.add_layout_pin_rect_center(text=pin_name,
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layer=pin.layer,
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offset=pin.center(),
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width=pin.width(),
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height=pin.height())
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def analytical_delay(self, corner, slew, load=0.0):
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""" Calculate the analytical delay of DFF-> INV -> INV """
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nand_delay = self.nand.analytical_delay(corner,
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slew=slew,
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load=self.inv.input_load())
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inv_delay = self.inv.analytical_delay(corner,
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slew=nand_delay.slew,
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load=load)
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return nand_delay + inv_delay
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