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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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e0b9989d852df4e71443915d430a43693e679254
OpenRAM/compiler/characterizer
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Hunter Nichols 91bbc556e8 Cleaned up control logic cycle creation in delay.py. Fixed bug which caused input data to be determined by the read ports.
2018-09-10 22:06:50 -07:00
..
__init__.py
Fix option reload problems and checkpointing so that it works properly.
2018-07-11 12:00:15 -07:00
charutils.py
Fix module import names for python3. Rename parse function to something meaningful.
2018-06-29 09:45:07 -07:00
delay.py
Cleaned up control logic cycle creation in delay.py. Fixed bug which caused input data to be determined by the read ports.
2018-09-10 22:06:50 -07:00
lib.py
Cleaned up control logic cycle creation in delay.py. Fixed bug which caused input data to be determined by the read ports.
2018-09-10 22:06:50 -07:00
setup_hold.py
Cleaned up control logic cycle creation in delay.py. Fixed bug which caused input data to be determined by the read ports.
2018-09-10 22:06:50 -07:00
stimuli.py
Remove code bloat and simplified port logic in some cases. Crashes while writing to lib.
2018-09-01 00:10:40 -07:00
trim_spice.py
Convert bitline index to integer in trim_spice
2018-07-26 14:29:44 -07:00
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