mirror of https://github.com/VLSIDA/OpenRAM.git
28 lines
711 B
Python
28 lines
711 B
Python
word_size = 2
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num_words = 16
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num_banks = 1
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tech_name = "freepdk45"
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output_path = "./temp"
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output_name = "sram_2_16_1_freepdk45"
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decoder = "hierarchical_decoder"
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ms_flop = "ms_flop"
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ms_flop_array = "ms_flop_array"
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control_logic = "control_logic"
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bitcell_array = "bitcell_array"
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sense_amp = "sense_amp"
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sense_amp_array = "sense_amp_array"
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precharge_array = "precharge_array"
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column_mux_array = "single_level_column_mux_array"
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write_driver = "write_driver"
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write_driver_array = "write_driver_array"
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tri_gate = "tri_gate"
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tri_gate_array = "tri_gate_array"
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wordline_driver = "wordline_driver"
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replica_bitline = "replica_bitline"
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replica_bitcell = "replica_bitcell"
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bitcell = "bitcell"
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delay_chain = "delay_chain"
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