mrg 4a40e96f6d Control logic route changes. ...

Move wl_en to top control signal.
Route wl_en directly to port_address.
Reorder input bus to bank.

2021-03-24 14:32:10 -07:00

..

sram_1bank.py

Control logic route changes.

2021-03-24 14:32:10 -07:00

sram_2bank.py

Update copyright year.

2021-01-22 11:23:28 -08:00

sram_base.py

Merge lekez2005 changes WITHOUT control logic change.

2021-03-01 15:19:30 -08:00

sram_config.py

Update copyright year.

2021-01-22 11:23:28 -08:00

sram.py

cleanup clutter

2021-03-01 15:23:57 +01:00