mirror of https://github.com/VLSIDA/OpenRAM.git
17 lines
567 B
Plaintext
17 lines
567 B
Plaintext
* SPICE3 file created from replica_cell_6t.ext - technology: scmos
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M1000 a_36_40# vdd vdd vdd pfet w=0.6u l=0.8u
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+ ad=0.76p pd=3.6u as=2.76p ps=12.4u
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** SOURCE/DRAIN TIED
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M1001 vdd a_36_40# vdd vdd pfet w=0.8u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M1002 a_36_40# vdd gnd gnd nfet w=1.6u l=0.4u
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+ ad=2.4p pd=7.2u as=4.48p ps=12u
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M1003 gnd a_36_40# vdd gnd nfet w=1.6u l=0.4u
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+ ad=0p pd=0u as=3.04p ps=10.4u
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M1004 a_36_40# wl bl gnd nfet w=0.8u l=0.4u
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+ ad=0p pd=0u as=0.8p ps=3.6u
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M1005 vdd wl br gnd nfet w=0.8u l=0.4u
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+ ad=0p pd=0u as=0.8p ps=3.6u
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C0 vdd 0 2.60fF
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