mirror of https://github.com/VLSIDA/OpenRAM.git
88 lines
2.6 KiB
Plaintext
88 lines
2.6 KiB
Plaintext
04_dummy_pbitcell_test.py
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04_pbitcell_test.py
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04_precharge_pbitcell_test.py
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04_replica_pbitcell_test.py
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04_single_level_column_mux_pbitcell_test.py
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05_bitcell_1rw_1r_array_test.py
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05_bitcell_array_test.py
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05_dummy_array_test.py
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05_pbitcell_array_test.py
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06_hierarchical_decoder_pbitcell_test.py
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06_hierarchical_decoder_test.py
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06_hierarchical_predecode2x4_pbitcell_test.py
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06_hierarchical_predecode2x4_test.py
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06_hierarchical_predecode3x8_pbitcell_test.py
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06_hierarchical_predecode3x8_test.py
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06_hierarchical_predecode4x16_test.py
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07_single_level_column_mux_array_pbitcell_test.py
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08_wordline_driver_array_pbitcell_test.py
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08_wordline_driver_array_test.py
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09_sense_amp_array_test_pbitcell.py
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09_sense_amp_array_test.py
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10_write_driver_array_pbitcell_test.py
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10_write_driver_array_test.py
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10_write_driver_array_wmask_pbitcell_test.py
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10_write_driver_array_wmask_test.py
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10_write_mask_and_array_pbitcell_test.py
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10_write_mask_and_array_test.py
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12_tri_gate_array_test.py
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14_replica_pbitcell_array_test.py
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14_replica_bitcell_array_test.py
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14_replica_column_test.py
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14_replica_column_1rw_1r_test.py
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18_port_address_test.py
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18_port_data_test.py
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18_port_data_wmask_test.py
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19_bank_select_pbitcell_test.py
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19_bank_select_test.py
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19_psingle_bank_test.py
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19_bank_select_pbitcell_test.py
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19_pmulti_bank_test.py
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19_multi_bank_test.py
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19_psingle_bank_test.py
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19_single_bank_1w_1r_test.py
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19_single_bank_wmask_1rw_1r_test.py
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19_single_bank_1rw_1r_test.py
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19_single_bank_test.py
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19_single_bank_wmask_test.py
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20_psram_1bank_2mux_1rw_1w_test.py
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20_psram_1bank_2mux_1rw_1w_wmask_test.py
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20_psram_1bank_2mux_1w_1r_test.py
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20_psram_1bank_2mux_test.py
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20_psram_1bank_4mux_1rw_1r_test.py
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20_sram_1bank_2mux_1w_1r_test.py
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20_sram_1bank_2mux_test.py
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20_sram_1bank_2mux_wmask_test.py
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20_sram_1bank_32b_1024_wmask_test.py
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20_sram_1bank_4mux_test.py
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20_sram_1bank_8mux_test.py
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20_sram_1bank_nomux_test.py
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20_sram_1bank_nomux_wmask_test.py
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20_sram_2bank_test.py
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21_hspice_delay_test.py
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21_hspice_setuphold_test.py
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21_model_delay_test.py
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21_ngspice_delay_test.py
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21_ngspice_setuphold_test.py
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22_psram_1bank_2mux_func_test.py
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22_psram_1bank_4mux_func_test.py
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22_psram_1bank_8mux_func_test.py
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22_psram_1bank_nomux_func_test.py
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22_sram_1bank_2mux_func_test.py
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22_sram_1bank_4mux_func_test.py
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22_sram_1bank_8mux_func_test.py
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22_sram_1bank_nomux_func_test.py
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22_sram_1rw_1r_1bank_nomux_func_test.py
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22_sram_wmask_func_test.py
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23_lib_sram_model_corners_test.py
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23_lib_sram_model_test.py
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23_lib_sram_prune_test.py
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23_lib_sram_test.py
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24_lef_sram_test.py
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25_verilog_sram_test.py
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26_hspice_pex_pinv_test.py
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26_ngspice_pex_pinv_test.py
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26_pex_test.py
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30_openram_back_end_test.py
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30_openram_front_end_test.py
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