mirror of https://github.com/VLSIDA/OpenRAM.git
5648 lines
242 KiB
Plaintext
5648 lines
242 KiB
Plaintext
VERSION 5.4 ;
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NAMESCASESENSITIVE ON ;
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BUSBITCHARS "[]" ;
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DIVIDERCHAR "/" ;
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UNITS
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dataBASE MICRONS 1000 ;
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END UNITS
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SITE MacroSite
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CLASS Core ;
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SIZE 12145.0 by 43967.5 ;
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END MacroSite
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MACRO sram_2_16_1_freepdk45
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CLASS BLOCK ;
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SIZE 12145.0 BY 43967.5 ;
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SYMMETRY X Y R90 ;
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SITE MacroSite ;
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PIN data[0]
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DIRECTION INOUT ;
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PORT
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LAYER metal2 ;
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RECT 10260.0 67.5 10330.0 207.5 ;
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END
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END data[0]
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PIN data[1]
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DIRECTION INOUT ;
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PORT
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LAYER metal2 ;
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RECT 10965.0 67.5 11035.0 207.5 ;
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END
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END data[1]
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PIN addr[0]
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DIRECTION INPUT ;
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PORT
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LAYER metal3 ;
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RECT 67.5 8370.0 837.5 8440.0 ;
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END
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END addr[0]
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PIN addr[1]
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DIRECTION INPUT ;
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PORT
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LAYER metal3 ;
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RECT 67.5 7665.0 837.5 7735.0 ;
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END
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END addr[1]
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PIN addr[2]
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DIRECTION INPUT ;
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PORT
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LAYER metal3 ;
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RECT 67.5 6960.0 837.5 7030.0 ;
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END
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END addr[2]
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PIN addr[3]
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DIRECTION INPUT ;
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PORT
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LAYER metal3 ;
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RECT 67.5 6255.0 837.5 6325.0 ;
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END
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END addr[3]
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PIN CSb
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DIRECTION INPUT ;
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PORT
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LAYER metal3 ;
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RECT -2987.5 23757.5 -2917.5 23897.5 ;
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END
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END CSb
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PIN WEb
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DIRECTION INPUT ;
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PORT
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LAYER metal3 ;
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RECT -2282.5 23757.5 -2212.5 23897.5 ;
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END
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END WEb
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PIN OEb
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DIRECTION INPUT ;
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PORT
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LAYER metal3 ;
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RECT -3692.5 23757.5 -3622.5 23897.5 ;
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END
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END OEb
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PIN clk
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DIRECTION INPUT ;
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PORT
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LAYER metal1 ;
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RECT -835.0 23757.5 -700.0 23947.5 ;
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END
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END clk
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PIN vdd
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DIRECTION INOUT ;
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USE POWER ;
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SHAPE ABUTMENT ;
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PORT
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LAYER metal2 ;
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RECT 452.5 67.5 732.5 44035.0 ;
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LAYER metal2 ;
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RECT 11932.5 67.5 12212.5 44035.0 ;
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LAYER metal1 ;
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RECT 67.5 452.5 12212.5 732.5 ;
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LAYER metal1 ;
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RECT 67.5 43755.0 12212.5 44035.0 ;
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END
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END vdd
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PIN gnd
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DIRECTION INOUT ;
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USE GROUND ;
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SHAPE ABUTMENT ;
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PORT
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LAYER metal2 ;
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RECT 67.5 67.5 347.5 44035.0 ;
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LAYER metal2 ;
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RECT 11547.5 67.5 11827.5 44035.0 ;
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LAYER metal1 ;
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RECT 67.5 67.5 12212.5 347.5 ;
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LAYER metal1 ;
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RECT 67.5 43370.0 12212.5 43650.0 ;
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END
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END gnd
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OBS
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LAYER metal1 ;
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END
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END sram_2_16_1_freepdk45
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END LIBRARY
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