mirror of https://github.com/VLSIDA/OpenRAM.git
21 lines
442 B
Python
21 lines
442 B
Python
word_size = 2
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num_words = 16
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num_rw_ports = 1
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num_r_ports = 1
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num_w_ports = 0
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tech_name = "scn4m_subm"
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nominal_corners_only = False
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process_corners = ["TT"]
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supply_voltages = [5.0]
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temperatures = [25]
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route_supplies = True
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check_lvsdrc = True
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output_path = "temp"
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output_name = "sram_1rw_1r_{0}_{1}_{2}".format(word_size,
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num_words,
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tech_name)
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