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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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de2dae40302007eb869101a04e56c55e17b9d94c
OpenRAM/compiler/custom
T
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Hunter Nichols b3500982ca Fixed issue with wire resistance in total resistance equations for cacti. Fixed issue with sense amp resistance values.
2021-08-04 16:10:27 -07:00
..
dff.py
Update copyright year.
2021-01-22 11:23:28 -08:00
inv_dec.py
Update copyright year.
2021-01-22 11:23:28 -08:00
nand2_dec.py
Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files.
2021-07-21 14:59:02 -07:00
nand3_dec.py
Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files.
2021-07-21 14:59:02 -07:00
nand4_dec.py
Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files.
2021-07-21 14:59:02 -07:00
sense_amp.py
Fixed issue with wire resistance in total resistance equations for cacti. Fixed issue with sense amp resistance values.
2021-08-04 16:10:27 -07:00
tri_gate.py
Update copyright year.
2021-01-22 11:23:28 -08:00
write_driver.py
Update copyright year.
2021-01-22 11:23:28 -08:00
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