mirror of https://github.com/VLSIDA/OpenRAM.git
275 lines
11 KiB
Python
275 lines
11 KiB
Python
import contact
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import pgate
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import debug
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from tech import drc, parameter, spice
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from vector import vector
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from globals import OPTS
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import logical_effort
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from sram_factory import factory
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class pnand3(pgate.pgate):
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"""
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This module generates gds of a parametrically sized 2-input nand.
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This model use ptx to generate a 2-input nand within a cetrain height.
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"""
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def __init__(self, name, size=1, height=None):
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""" Creates a cell for a simple 3 input nand """
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pgate.pgate.__init__(self, name, height)
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debug.info(2, "create pnand3 structure {0} with size of {1}".format(name, size))
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self.add_comment("size: {}".format(size))
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# We have trouble pitch matching a 3x sizes to the bitcell...
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# If we relax this, we could size this better.
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self.size = size
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self.nmos_size = 2*size
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self.pmos_size = parameter["beta"]*size
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self.nmos_width = self.nmos_size*drc("minwidth_tx")
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self.pmos_width = self.pmos_size*drc("minwidth_tx")
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# FIXME: Allow these to be sized
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debug.check(size==1,"Size 1 pnand3 is only supported now.")
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self.tx_mults = 1
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def add_pins(self):
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""" Adds pins for spice netlist """
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self.add_pin_list(["A", "B", "C", "Z", "vdd", "gnd"])
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def create_netlist(self):
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self.add_pins()
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self.add_ptx()
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self.create_ptx()
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def create_layout(self):
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""" Calls all functions related to the generation of the layout """
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self.setup_layout_constants()
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self.route_supply_rails()
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self.place_ptx()
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self.connect_rails()
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self.add_well_contacts()
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self.extend_wells(self.well_pos)
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self.route_inputs()
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self.route_output()
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def add_ptx(self):
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""" Create the PMOS and NMOS transistors. """
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self.nmos = factory.create(module_type="ptx",
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width=self.nmos_width,
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mults=self.tx_mults,
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tx_type="nmos",
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connect_poly=True,
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connect_active=True)
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self.add_mod(self.nmos)
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self.pmos = factory.create(module_type="ptx",
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width=self.pmos_width,
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mults=self.tx_mults,
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tx_type="pmos",
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connect_poly=True,
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connect_active=True)
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self.add_mod(self.pmos)
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def setup_layout_constants(self):
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""" Pre-compute some handy layout parameters. """
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# Compute the overlap of the source and drain pins
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self.overlap_offset = self.pmos.get_pin("D").ll() - self.pmos.get_pin("S").ll()
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# Two PMOS devices and a well contact. Separation between each.
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# Enclosure space on the sides.
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self.well_width = 3*self.pmos.active_width + self.pmos.active_contact.width \
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+ 2*drc("active_to_body_active") + 2*drc("well_enclosure_active") \
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- self.overlap_offset.x
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self.width = self.well_width
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# Height is an input parameter, so it is not recomputed.
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# This will help with the wells and the input/output placement
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self.output_pos = vector(0,0.5*self.height)
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# This is the extra space needed to ensure DRC rules to the active contacts
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nmos = factory.create(module_type="ptx", tx_type="nmos")
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extra_contact_space = max(-nmos.get_pin("D").by(),0)
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# This is a poly-to-poly of a flipped cell
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self.top_bottom_space = max(0.5*self.m1_width + self.m1_space + extra_contact_space,
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drc("poly_extend_active"), self.poly_space)
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def route_supply_rails(self):
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""" Add vdd/gnd rails to the top and bottom. """
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self.add_layout_pin_rect_center(text="gnd",
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layer="metal1",
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offset=vector(0.5*self.width,0),
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width=self.width)
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self.add_layout_pin_rect_center(text="vdd",
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layer="metal1",
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offset=vector(0.5*self.width,self.height),
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width=self.width)
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def create_ptx(self):
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"""
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Create the PMOS and NMOS in the netlist.
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"""
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self.pmos1_inst=self.add_inst(name="pnand3_pmos1",
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mod=self.pmos)
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self.connect_inst(["vdd", "A", "Z", "vdd"])
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self.pmos2_inst = self.add_inst(name="pnand3_pmos2",
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mod=self.pmos)
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self.connect_inst(["Z", "B", "vdd", "vdd"])
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self.pmos3_inst = self.add_inst(name="pnand3_pmos3",
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mod=self.pmos)
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self.connect_inst(["Z", "C", "vdd", "vdd"])
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self.nmos1_inst=self.add_inst(name="pnand3_nmos1",
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mod=self.nmos)
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self.connect_inst(["Z", "C", "net1", "gnd"])
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self.nmos2_inst=self.add_inst(name="pnand3_nmos2",
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mod=self.nmos)
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self.connect_inst(["net1", "B", "net2", "gnd"])
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self.nmos3_inst=self.add_inst(name="pnand3_nmos3",
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mod=self.nmos)
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self.connect_inst(["net2", "A", "gnd", "gnd"])
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def place_ptx(self):
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"""
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Place the PMOS and NMOS in the layout at the upper-most and lowest position
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to provide maximum routing in channel
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"""
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pmos1_pos = vector(self.pmos.active_offset.x,
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self.height - self.pmos.active_height - self.top_bottom_space)
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self.pmos1_inst.place(pmos1_pos)
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pmos2_pos = pmos1_pos + self.overlap_offset
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self.pmos2_inst.place(pmos2_pos)
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self.pmos3_pos = pmos2_pos + self.overlap_offset
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self.pmos3_inst.place(self.pmos3_pos)
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nmos1_pos = vector(self.pmos.active_offset.x, self.top_bottom_space)
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self.nmos1_inst.place(nmos1_pos)
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nmos2_pos = nmos1_pos + self.overlap_offset
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self.nmos2_inst.place(nmos2_pos)
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self.nmos3_pos = nmos2_pos + self.overlap_offset
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self.nmos3_inst.place(self.nmos3_pos)
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# This should be placed at the top of the NMOS well
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self.well_pos = vector(0,self.nmos1_inst.uy())
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def add_well_contacts(self):
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""" Add n/p well taps to the layout and connect to supplies """
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self.add_nwell_contact(self.pmos, self.pmos3_pos)
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self.add_pwell_contact(self.nmos, self.nmos3_pos)
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def connect_rails(self):
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""" Connect the nmos and pmos to its respective power rails """
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self.connect_pin_to_rail(self.nmos1_inst,"S","gnd")
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self.connect_pin_to_rail(self.pmos1_inst,"S","vdd")
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self.connect_pin_to_rail(self.pmos2_inst,"D","vdd")
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def route_inputs(self):
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""" Route the A and B inputs """
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# wire space or wire and one contact space
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metal_spacing = max(self.m1_space + self.m1_width, self.m2_space + self.m2_width,
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self.m1_space + 0.5*contact.poly.width + 0.5*self.m1_width)
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active_spacing = max(self.m1_space, 0.5*contact.poly.first_layer_width + drc("poly_to_active"))
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inputC_yoffset = self.nmos3_pos.y + self.nmos.active_height + active_spacing
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self.route_input_gate(self.pmos3_inst, self.nmos3_inst, inputC_yoffset, "C", position="center")
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inputB_yoffset = inputC_yoffset + metal_spacing
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self.route_input_gate(self.pmos2_inst, self.nmos2_inst, inputB_yoffset, "B", position="center")
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self.inputA_yoffset = inputB_yoffset + metal_spacing
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self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.inputA_yoffset, "A", position="center")
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def route_output(self):
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""" Route the Z output """
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# PMOS1 drain
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pmos1_pin = self.pmos1_inst.get_pin("D")
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# PMOS3 drain
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pmos3_pin = self.pmos3_inst.get_pin("D")
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# NMOS3 drain
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nmos3_pin = self.nmos3_inst.get_pin("D")
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# Go up to metal2 for ease on all output pins
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self.add_contact_center(layers=("metal1", "via1", "metal2"),
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offset=pmos1_pin.center())
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self.add_contact_center(layers=("metal1", "via1", "metal2"),
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offset=pmos3_pin.center())
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self.add_contact_center(layers=("metal1", "via1", "metal2"),
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offset=nmos3_pin.center())
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# PMOS3 and NMOS3 are drain aligned
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self.add_path("metal2",[pmos3_pin.bc(), nmos3_pin.uc()])
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# Route in the A input track (top track)
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mid_offset = vector(nmos3_pin.center().x,self.inputA_yoffset)
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self.add_path("metal2",[pmos1_pin.bc(), mid_offset, nmos3_pin.uc()])
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# This extends the output to the edge of the cell
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self.add_contact_center(layers=("metal1", "via1", "metal2"),
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offset=mid_offset)
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self.add_layout_pin_rect_center(text="Z",
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layer="metal1",
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offset=mid_offset,
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width=contact.m1m2.first_layer_width,
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height=contact.m1m2.first_layer_height)
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def input_load(self):
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return ((self.nmos_size+self.pmos_size)/parameter["min_tx_size"])*spice["min_tx_gate_c"]
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def analytical_delay(self, corner, slew, load=0.0):
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r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"])
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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return self.cal_delay_with_rc(corner, r = r, c = c_para+load, slew = slew)
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def analytical_power(self, proc, vdd, temp, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_rate"]
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power_dyn = c_eff*vdd*vdd*freq
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power_leak = spice["nand3_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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transition_prob = spice["nand3_transition_prob"]
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return transition_prob*(c_load + c_para)
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def get_cin(self):
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"""Return the relative input capacitance of a single input"""
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return self.nmos_size+self.pmos_size
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def get_stage_effort(self, cout, inp_is_rise=True):
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"""Returns an object representing the parameters for delay in tau units.
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Optional is_rise refers to the input direction rise/fall. Input inverted by this stage.
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"""
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parasitic_delay = 3
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return logical_effort.logical_effort(self.name, self.size, self.get_cin(), cout, parasitic_delay, not inp_is_rise)
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