This website requires JavaScript.
Explore
Help
Sign In
luke
/
OpenRAM
Watch
1
Star
0
Fork
0
mirror of
https://github.com/VLSIDA/OpenRAM.git
synced
2026-08-29 17:39:02 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
dc20bf9e114780390aef6b65b34f02f374ed0a66
OpenRAM
/
technology
/
freepdk45
T
History
Hunter Nichols
97fc37aec1
Added checks for the bitline voltage at sense amp enable 50%.
2018-12-12 23:59:32 -08:00
..
gds_lib
Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
lib
RELEASE 1.0
2016-11-08 09:57:35 -08:00
sp_lib
Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
tech
Added checks for the bitline voltage at sense amp enable 50%.
2018-12-12 23:59:32 -08:00
tf
Change layer text to comment to avoid glade reserved keyword
2018-11-02 10:58:00 -07:00
layers.map
RELEASE 1.0
2016-11-08 09:57:35 -08:00