Bugra Onal 2b79646b8f Merge branch 'dev' into char

2022-10-04 09:09:52 -07:00

..

__init__.py

Use packages for imports.

2022-07-13 15:55:57 -07:00

channel_route.py

Use packages for imports.

2022-07-13 15:55:57 -07:00

contact.py

Use packages for imports.

2022-07-13 15:55:57 -07:00

delay_data.py

Update copyright year.

2021-01-22 11:23:28 -08:00

design.py

Initial work on separate delay and func simulation

2022-08-10 12:06:14 -07:00

errors.py

Add exception errors file

2020-04-08 16:55:45 -07:00

geometry.py

Remove line ending whitespace

2022-07-22 19:52:38 +03:00

hierarchy_design.py

Use packages for imports.

2022-07-13 15:55:57 -07:00

hierarchy_layout.py

Fix print errors in code format unit test.

2022-07-26 12:20:15 -07:00

hierarchy_spice.py

Use packages for imports.

2022-07-13 15:55:57 -07:00

lef.py

Remove line ending whitespace

2022-07-22 19:52:38 +03:00

logical_effort.py

Use packages for imports.

2022-07-13 15:55:57 -07:00

pin_layout.py

Remove line ending whitespace

2022-07-22 19:52:38 +03:00

power_data.py

Update copyright year.

2021-01-22 11:23:28 -08:00

route.py

Use packages for imports.

2022-07-13 15:55:57 -07:00

timing_graph.py

Added graph store and read functionality

2022-08-30 09:15:35 -07:00

utils.py

Remove line ending whitespace

2022-07-22 19:52:38 +03:00

vector3d.py

Use packages for imports.

2022-07-13 15:55:57 -07:00

vector.py

Fix missing hash recompute in vector class.

2022-05-17 13:30:41 -07:00

verilog.py

Further fixes for new verilog naming convention

2022-08-18 11:03:13 -07:00

wire_path.py

Use packages for imports.

2022-07-13 15:55:57 -07:00

wire_spice_model.py

Added unit r and c values with m2 minwidth incorporated to match CACTI params

2021-08-01 00:23:59 -07:00

wire.py

Remove line ending whitespace

2022-07-22 19:52:38 +03:00