mirror of https://github.com/VLSIDA/OpenRAM.git
52 lines
2.0 KiB
Python
52 lines
2.0 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
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# All rights reserved.
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#
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from openram import debug
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from openram.base import vector
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from openram.base import contact
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from openram.sram_factory import factory
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from openram.tech import drc, spice
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from openram.tech import cell_properties as props
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from openram import OPTS
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from openram.modules.capped_replica_bitcell_array import capped_replica_bitcell_array
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from .sky130_bitcell_base_array import sky130_bitcell_base_array
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class sky130_capped_replica_bitcell_array(capped_replica_bitcell_array, sky130_bitcell_base_array):
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"""
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Creates a replica bitcell array then adds the row and column caps to all
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sides of a bitcell array.
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"""
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def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
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super().__init__(rows, cols, rbl, left_rbl, right_rbl, name)
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def add_layout_pins(self):
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for used_name, base_name in zip(self.used_wordline_names, self.dummy_col_insts[0].mod.all_wordline_names):
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pin = self.dummy_col_insts[0].get_pin(base_name)
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pin_offset = pin.ll().scale(0, 1)
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pin_width = self.width
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pin_height = pin.height()
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self.add_layout_pin(text=used_name,
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layer=pin.layer,
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offset=pin_offset,
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width=pin_width,
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height=pin_height)
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for used_name, pin_name in zip(self.bitline_pin_list, self.dummy_row_insts[0].mod.all_bitline_names):
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pin = self.dummy_row_insts[0].get_pin(pin_name)
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pin_offset = pin.ll().scale(1, 0)
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pin_width = pin.width()
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pin_height = self.height
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self.add_layout_pin(text=used_name,
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layer=pin.layer,
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offset=pin_offset,
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width=pin_width,
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height=pin_height)
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