mirror of https://github.com/VLSIDA/OpenRAM.git
586 lines
17 KiB
BibTeX
586 lines
17 KiB
BibTeX
@Comment @string{DAC = "ACM/IEEE Design Automation Conference~(DAC)"}
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@Comment @string{TDEV = "IEEE Transactions on Electron Devices"}
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@Comment @string{DATE = "IEEE Design, Automation and Test in Europe~(DATE)"}
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@Comment @string{ISSCC = "IEEE International Solid-State Circuits Conference~(ISSCC)"}
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@Comment @string{TVLSI = "IEEE Transactions on Very Large Scale Integration~(VLSI) Systems"}
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@Comment @string{JSSC = "IEEE Journal of Solid-State Circuits~(JSSC)"}
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@Comment @string{ICCD = "International Conference on Computer Design~(ICCD)"}
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@Comment @string{ISLPED = "IEEE International Symposium on Low Power Electronics and Design~(ISLPED)"}
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@Comment @STRING{ICCAD = "IEEE/ACM International Conference on Computer-Aided Design~(ICCAD)"}
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@Comment @string{ASP-DAC = "IEEE Asia and South Pacific Design Automation Conference~(ASP-DAC)"}
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@Comment @string{ISCAS = "IEEE International Symposium on Circuits and Systems~(ISCAS)"}
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@Comment @string{TCAD = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems~(TCAD)"}
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@Comment @string{GLSVLSI = "ACM Great Lakes Symposium on VLSI~(GLSVLSI)"}
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@Comment @string{TCASI = "IEEE Transactions on Circuits and Systems I~(TCAS-I)"}
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@Comment @string{TCASII = "IEEE Transactions on Circuits and Systems II~(TCAS-II)"}
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@Comment @string{TC = "IEEE Transactions on Computers"}
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@Comment @string{ISPD = "IEEE International Symposium on Physical Design~(ISPD)"}
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@Comment @string{TODAES = "ACM Transactions on Design Automation of Electronic Systems~(TODAES)"}
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@Comment @string{ISVLSI = "IEEE International Symposium on Very Large Scale Integration~(ISVLSI)"}
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@Comment @string{ISQED = "International Symposium on Quality Electronic Design~(ISQED)"}
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@Comment @string{TNUKE = "IEEE Transactions on Nuclear Science"}
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@Comment @string{MWSCAS = "IEEE Midwest Symposium on Circuits and Systems~(MWSCAS)"}
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@Comment @string{MSE = "IEEE International Conference on Microelectronic Systems Education~(MSE)"}
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@string{DAC = "DAC"}
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@string{TDEV = "TDEV"}
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@string{DATE = "DATE"}
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@string{ISSCC = "ISSCC"}
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@string{TVLSI = "TVLSI"}
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@string{JSSC = "JSSC"}
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@string{ICCD = "ICCD"}
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@string{ISLPED = "ISLPED"}
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@STRING{ICCAD = "ICCAD"}
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@string{ASP-DAC = "ASP-DAC"}
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@string{ISCAS = "ISCAS"}
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@string{TCAD = "TCAD"}
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@string{GLSVLSI = "GLSVLSI"}
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@string{TCASI = "TCAS-I"}
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@string{TCASII = "TCAS-II"}
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@string{TC = "TCOMP"}
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@string{ISPD = "ISPD"}
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@string{TODAES = "TODAES"}
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@string{ISVLSI = "ISVLSI"}
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@string{ISQED = "ISQED"}
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@string{TNUKE = "Trans. on Nuclear Science"}
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@string{MWSCAS = "MWSCAS"}
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@string{MSE = "MSE"}
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@book{Rabaey:2003,
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title = {Digital Integrated Circuits: A Design Perspective},
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author = {J. Rabaey and A. Chandrakasan and B. Nikolić},
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year = {2003},
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publisher = {Pearson Education, Inc.},
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edition = {2nd}
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}
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@book{Chandrakasan:2001,
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title = {Design of High Performance Microprocessor Circuits},
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booktitle = {Design of High Performance Microprocessor Circuits},
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author = {A. Chandrakasan and W.J. Bowhill and F. Fox},
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year = {2001},
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publisher = {IEEE Press}
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}
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@manual{gdsmill,
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title = {GDS Mill User Manual},
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author = {M. Wieckowski},
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year = {2010}
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}
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%these are end of chapter references from Rabaey
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%%%%%%%%%%%
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@article{Amrutur:2001,
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author = {B.S. Amrutur and M.A. Horowitz},
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journal = JSSC,
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title = {Fast Low-Power Decoders for RAMs},
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number = {10},
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pages = {1506-1515},
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volume = {36},
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year = {2001},
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month = {Oct}
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}
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@inbook{Preston:2001,
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title = {Register Files and Caches},
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author = {R.P. Preston},
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crossref = {Chandrakasan:2001}
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}
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@book{Itoh:2001,
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title = {VLSI Memory Chip Design},
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author = {K. Itoh},
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publisher = {Springer-Verlag},
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year = {2001}
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}
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@article{Itoh:1990,
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author = {K. Itoh},
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journal = JSSC,
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title = {Trends in Megabit DRAM Circuit Design},
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number = {3},
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pages = {778-798},
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volume = {25},
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year = {1990},
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month = {Jun}
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}
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@article{May:1979,
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author = {T. May and M. Woods},
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journal = TDEV,
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title = {Aplha-Particle-Induced Soft Errors in Dynamic Memories},
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number = {1},
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pages = {2-9},
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volume = {26},
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year = {1979},
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month = {Jan}
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}
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@ARTICLE{Tosaka:1997,
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author={Y. Tosaka and S. Satoh and T. Itakura and K. Suzuki and T. Sugii and H. Ehara and G.A. Woffinden},
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journal=TDEV,
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title={Cosmic Ray Neutron-Induced Soft Errors in Sub-Half Micron CMOS Circuits},
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year={1997},
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volume={18},
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number={3},
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pages={99-101}
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}
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@ARTICLE{Regitz:1970,
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author={W.M. Regitz and J. Karp},
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journal=JSSC,
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title={Three-transistor-cell 1024-bit 500-ns MOS RAM},
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year={1970},
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volume={5},
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number={5},
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pages={181-186}
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}
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@INPROCEEDINGS{Kim1:2011,
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author={S. Kim and M. Guthaus},
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booktitle=DAC,
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title={Leakage-aware redundancy for reliable sub-threshold memories},
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year={2011},
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pages={435-440}
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}
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@INPROCEEDINGS{Kim2:2011,
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author={S. Kim and M. Guthaus},
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booktitle=VLSISOC,
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title={SNM-aware power reduction and reliability improvement in 45nm {SRAM}s},
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year={2011},
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pages={204-207}
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}
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@INPROCEEDINGS{Kim3:2011,
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author={S. Kim and M. Guthaus},
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booktitle=ICCAD,
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title={Low-power multiple-bit upset tolerant memory optimization},
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year={2011},
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pages={577-581}
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}
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@INPROCEEDINGS{Kim:2012,
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author={S. Kim and M. Guthaus},
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booktitle=VLSISOC,
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title={Dynamic voltage scaling for SEU-tolerance in low-power memories},
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year={2012},
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pages={207-212}
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}
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@ARTICLE{Rusu:2003,
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author={S. Rusu and J. Stinson and S. Tam and J. Leung and H. Muljono and B. Cherkauer},
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journal=JSSC,
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title={A 1.5-GHz 130-nm Itanium reg; 2 Processor with 6-MB on-die L3 cache},
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year={2003},
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volume={38},
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number={11},
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pages={1887-1895}
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}
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@article{itrs:2012,
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author = {International Technology Roadmap for Semiconductors},
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title = {2012 ITRS Report: System Drivers},
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howpublished = {www.itrs.net},
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year = {2012}
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}
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@article{Kurdahi:2006,
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author = {F.J. Kurdahi and A.M. Eltawil and Y.H. Park and R.N Kanj and S.R. Nassif},
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journal = ISQED,
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title = {System-level {SRAM} Yield Enhancement},
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year = {2006},
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month = {Mar}
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}
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@misc{i7:2011,
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author = {A. Shimpi},
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title = {Intel Core i7 3960X (Sandy Bridge) Review: Keeping the High-End Alive},
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howpublished = {\url{http://www.anandtech.com/show/5091/intel-core-i7-3960x-sandy-bridge-e-review-keeping-the-high-end-alive}},
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year = {2011},
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month = {Nov}
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}
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@misc{calibre:2013,
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author = {Mentor Graphics},
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title = {Calibre nmDRC and nmLVS},
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howpublished = {\url{http://www.mentor.com/products/ic_nanometer_design/verification-signoff/physical-verification/}},
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year = {2013}
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}
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@misc{hspice:2013,
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author = {Synopsis},
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title = {HSPICE},
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howpublished = {\url{http://www.synopsys.com/tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Pages/default.aspx}},
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year = {2013}
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}
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@INPROCEEDINGS{Athe:2009,
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author={P. Athe and S. Dasgupta},
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booktitle={{ISIEA}},
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title={A comparative study of 6T, 8T and 9T decanano {SRAM} cell},
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year={2009},
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volume={2},
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pages={889-894}
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}
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@ARTICLE{Calin:1996,
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author={T. Calin and M. Nicolaidis and R. Velazco},
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journal=TNUKE,
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title={Upset hardened memory design for submicron CMOS technology},
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year={1996},
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volume={43},
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number={6},
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pages={2874-2878}
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}
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@INPROCEEDINGS{Jung:2012,
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author={I. Jung and Y. Kim and F. Lombardi},
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booktitle=MWSCAS,
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title={A novel sort error hardened 10T {SRAM} cells for low voltage operation},
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year={2012},
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pages={714-717}
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}
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@ARTICLE{Goudarzi:2010,
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author={M. Goudarzi and T. Ishihara},
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journal=TVLSI,
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title={{SRAM} Leakage Reduction by Row/Column Redundancy Under Random Within-Die Delay Variation},
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year={2010},
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volume={18},
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number={12},
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pages={1660-1671}
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}
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@techreport{ibm:1997,
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author = {IBM},
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title = {Understanding Static RAM Operation},
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howpublished = {IBM Applications Note},
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year = {1997},
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month = {Mar}
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}
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@misc{python:2013,
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author = {Python},
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title = {The Python Programming Language},
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howpublished = {\url{http://www.python.org}},
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year = {2013}
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}
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@misc{Wieckowski:2010,
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author = {Michael Wieckowski},
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title = {GDS Mill},
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howpublished = {\url{http://michaelwieckowski.com/?page_id=190}},
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year = {2010}
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}
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@misc{globalfoundries:2015,
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author = {{Global Foundries}},
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title = {{ASICs}},
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howpublished = {\url{http://www.globalfoundries.com/technology-solutions/asics}},
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year = {2015}
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}
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@misc{synopsys:2015,
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author = {Synopsys},
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title = {DesignWare Memory Compilers},
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howpublished = {\url{http://www.synopsys.com/dw/ipdir.php?ds=dwc_sram_memory_compilers}},
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year = {2015}
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}
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@misc{dolphin:2015,
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author = {{Dolphin Technology}},
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title = {Memory Products},
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howpublished = {\url{http://www.dolphin-ic.com/memory-products.html}},
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year = {2015}
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}
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@misc{faraday:2015,
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author = {{Faraday Technologies}},
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title = {Memory Compiler Architecture},
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howpublished = {\url{http://www.faraday-tech.com/html/Product/IPProduct/LibraryMemoryCompiler/index.htm}},
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year = {2015}
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}
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@misc{arm:2015,
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author = {ARM},
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title = {Embedded Memory {IP}},
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howpublished = {\url{http://www.arm.com/products/physical-ip/embedded-memory-ip/index.php}},
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year = {2015}
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}
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@misc{scmos,
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author = {MOSIS},
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title = {{MOSIS} Scalable {CMOS} ({SCMOS})},
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howpublished = {\url{https://www.mosis.com/files/scmos/scmos.pdf}},
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year = {2015}
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}
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%%%look at this paper
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@article{Hanson:2008,
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author = {S. Hanson and M. Seok and D. Sylvester and D. Blaauw},
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journal = TDEV,
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title = {Nanometer device scaling in subthreshold logic and {SRAM}},
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number = {1},
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pages = {175-185},
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volume = {55},
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year = {2008}
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}
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%%%look at this paper
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@article{Baeg:2009,
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author={S. Baeg and S. Wen and R. Wong},
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journal=TNUKE,
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title={{SRAM} Interleaving Distance Selection With a Soft Error Failure Model},
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year={2009},
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month={Aug.},
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volume={56},
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number={4},
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pages={2111-2118}
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}
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%%%look at this paper
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@article{Amrutur:2001,
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author={B. Amrutur and M. Horowitz},
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journal=JSSC,
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title={Fast low-power decoders for {RAMs}},
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year={2001},
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month={Oct},
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volume={36},
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number={10},
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pages={1506-1515}
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}
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@inproceedings{Chen:2012,
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author={Chen Ming and Bai Na},
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booktitle={{CyberC}},
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title={An Efficient and Flexible Embedded Memory {IP} Compiler},
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year={2012},
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month={Oct},
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pages={268-273},
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keywords={SRAM chips;embedded systems;interpolation;polynomials;circuit structure;efficient embedded memory IP compiler;flexible embedded memory IP compiler;polynomial interpolation algorithm;single-port SRAM compiler;Integrated circuit modeling;Interpolation;Mathematical model;Memory management;Random access memory;Tiles;Timing;SRAM;interpolation;memory compiler;modeling;tiling},
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doi={10.1109/CyberC.2012.52}
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}
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@inproceedings{Wu:2010,
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author={Sheng Wu and Xiang Zheng and Zhiqiang Gao and Xiangqing He},
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booktitle={{DDECS}},
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title={A 65nm embedded low power {SRAM} compiler},
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year={2010},
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month={April},
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pages={123-124},
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keywords={CMOS technology;Design methodology;Helium;Kernel;Layout;Libraries;Microelectronics;Program processors;Random access memory;SRAM chips;SRAM compiler;SoC IP;low power},
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doi={10.1109/DDECS.2010.5491802}
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}
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@inproceedings{Xu:2007,
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author={Yi Xu and Zhiqiang Gao and Xiangqing He},
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booktitle=ISCAS,
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title={A Flexible Embedded {SRAM} {IP} Compiler},
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year={2007},
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month={May},
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pages={3756-3759},
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keywords={SRAM chips;circuit layout CAD;elemental semiconductors;embedded systems;logic design;program compilers;silicon;Si;atatic random access memory;block assembly techniques;embedded SRAM IP compiler;physical data syntax;silicon compiler;Assembly;Capacitance;Circuits;Energy consumption;Graphical user interfaces;Helium;Microelectronics;Random access memory;SRAM chips;Silicon compiler},
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doi={10.1109/ISCAS.2007.378778}
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}
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%%%%Newest memory compiler on market in 2014
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@inproceedings{Goldman:2014,
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author={Goldman, R. and Bartleson, K. and Wood, T. and Melikyan, V. and Babayan, E.},
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booktitle={{EWME}},
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title={Synopsys' Educational Generic Memory Compiler},
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year={2014},
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month={May},
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pages={89-92},
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keywords={SRAM chips;courseware;electronic engineering computing;electronic engineering education;GMC software tool;Synopsys educational generic memory compiler software tool;automatic SRAM cell generation;automatic static RAM cell generation;educational designs;educational process;intellectual property restrictions;Educational institutions;Layout;Memory management;Multiplexing;Ports (Computers);Random access memory;Software},
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doi={10.1109/EWME.2014.6877402}
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}
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@mastersthesis{butera:2013,
|
|
author = {J. Butera},
|
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title = {OpenRAM: An Open-Source Memory Compiler},
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school = {University of California - Santa Cruz},
|
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year = {2013}
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}
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@inproceedings{johannsen:blocks,
|
|
author = {D. Jahannsen},
|
|
title = {Bristle Blocks: A Silicon Compiler},
|
|
booktitle = DAC,
|
|
pages = {195-198},
|
|
year = {1979}
|
|
}
|
|
|
|
@book{broderson:sicompiler,
|
|
author = {R. Broderson},
|
|
title = {Anatomy of a Silicon Compiler},
|
|
publisher = {Springer},
|
|
year = {1992}
|
|
}
|
|
|
|
@inproceedings{poechmueller:array,
|
|
author = {P. Poechmueller and G.~K. Sharma and M. Glesner},
|
|
title = {A {CAD} Tool for Designing Large, Fault-Tolerant {VLSI} Arrays},
|
|
booktitle = GLSVLSI,
|
|
year = {1991}
|
|
}
|
|
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@inproceedings{huang:array,
|
|
author = {T.-H. Huang and C.-M. Liu and C.-W. Jen},
|
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title = {A High-Level Synthesizer for {VLSI} Array Architectures Dedicated to Digital Signal Processing},
|
|
booktitle = {International Conference on Acoustics, Speech and Signal Processing},
|
|
pages = {1221-1224},
|
|
year = {1991}
|
|
}
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@article{cabe:flexible,
|
|
author = {AC Cabe and Z Qi and W Huang and Y Zhang and MR Stan and GS Rose},
|
|
journal = {Cadence CDNLive},
|
|
title = {A flexible, technology adaptive memory generation tool},
|
|
year = {2006},
|
|
}
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|
|
@mastersthesis{fabmem:2010,
|
|
author = {T. Shah},
|
|
title = {{FabMem}: A Multiported {RAM} and {CAM} Compiler for Superscalar Design Space Exploration},
|
|
school = {North Carolina State University},
|
|
year = {2010}
|
|
}
|
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|
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@misc{virage:2015,
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|
author = {{Virage Logic}},
|
|
title = {{SiWare} Memory},
|
|
howpublished = {\url{http://www.viragelogic.com}},
|
|
year = {2015}
|
|
}
|
|
|
|
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|
@article{RBL:1998,
|
|
author = {B. S. Amrutur and M. A. Horowitz},
|
|
journal = JSSC,
|
|
title = {A Replica Technique for Wordline and Sense Control in Low-Power {SRAM}s},
|
|
number = {8},
|
|
pages = {1208-1219},
|
|
volume = {33},
|
|
year = {1998},
|
|
month = {Aug}
|
|
}
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% references for bit-density comparison
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@article{Bit_Density_1,
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author = {K. Kushida and others},
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journal = JSSC,
|
|
title = {A 0.7 {V} Single-Supply {SRAM} With 0.495 $um^2$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme},
|
|
number = {4},
|
|
pages = {1192-1198},
|
|
volume = {44},
|
|
year = {2009},
|
|
month = {Apr}
|
|
}
|
|
|
|
|
|
@article{Bit_Density_2,
|
|
author = {Sh. Miyano and others},
|
|
journal = JSSC,
|
|
title = {Highly Energy-Efficient {SRAM} With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges},
|
|
number = {4},
|
|
pages = {924-931},
|
|
volume = {48},
|
|
year = {2013},
|
|
month = {Apr}
|
|
}
|
|
|
|
@article{Bit_Density_3,
|
|
author = {S. O. Toh and Zh. Guo and T. K. Liu and B. Nikolic},
|
|
journal = JSSC,
|
|
title = {Characterization of Dynamic {SRAM} Stability in 45 nm {CMOS}},
|
|
number = {11},
|
|
pages = {2702-2712},
|
|
volume = {46},
|
|
year = {2011},
|
|
month = {Nov}
|
|
}
|
|
|
|
@article{Bit_Density_4,
|
|
author = {K. Yamaguchi and others},
|
|
journal = JSSC,
|
|
title = {A 1.5-ns Access Time, 78- $um^2$ Memory-Cell Size, 64-kb {ECL-CMOS SRAM}},
|
|
number = {2},
|
|
pages = {167-174},
|
|
volume = {27},
|
|
year = {1992},
|
|
month = {Feb}
|
|
}
|
|
|
|
@article{Bit_Density_5,
|
|
author = {N. Shibata and H. Morimura and M. Watanabe},
|
|
journal = JSSC,
|
|
title = {A {1-V}, {10-MHz}, 3.5-mW, {1-Mb} {MTCMOS SRAM} with Charge-Recycling Input/Output Buffers},
|
|
number = {6},
|
|
pages = {866-877},
|
|
volume = {34},
|
|
year = {1999},
|
|
month = {Jun}
|
|
}
|
|
|
|
@article{Bit_Density_6,
|
|
author = {N. Tamba and others},
|
|
journal = JSSC,
|
|
title = {A 1.5-ns 256-kb {BiCMOS SRAM} with 60-ps 11-K Logic Gates},
|
|
number = {11},
|
|
pages = {1344-1352},
|
|
volume = {48},
|
|
year = {1994},
|
|
month = {Nov}
|
|
}
|
|
|
|
%author={Yamaguchi, K. and Nambu, H. and Kanetani, K. and Idei, Y. and Homma, N. and Hiramoto, T. and Tamba, N. and Watanabe, K. and Odaka, Masanori and Ikeda, T. and Ohhata, K. and Sakurai, Y.},
|
|
@ARTICLE{127339,
|
|
author={Yamaguchi, K. and others},
|
|
journal=JSSC,
|
|
title={A $1.5$-ns access time, $78~um^2$ memory-cell size, $64$-kb {ECL-CMOS SRAM}},
|
|
year={1992},
|
|
volume={27},
|
|
number={2},
|
|
pages={167-174},
|
|
doi={10.1109/4.127339},
|
|
ISSN={0018-9200},
|
|
month={Feb},
|
|
}
|
|
|
|
%author={Kushida, K. and Suzuki, A. and Fukano, G. and Kawasumi, A. and Hirabayashi, O. and Takeyama, Y. and Sasaki, T. and Katayama, A. and Fujimura, Y. and Yabe, T.},
|
|
@INPROCEEDINGS{4585946,
|
|
author={Kushida, K. and others},
|
|
booktitle=ISVLSI,
|
|
title={A $0.7$V single-supply {SRAM} with $0.495~um^2$ cell in $65$nm technology
|
|
utilizing self-write-back sense amplifier and cascaded bit
|
|
line scheme},
|
|
year={2008},
|
|
pages={46-47},
|
|
doi={10.1109/VLSIC.2008.4585946},
|
|
month={June}
|
|
}
|
|
|
|
%author={Stine, J.E. and Castellanos, I. and Wood, M. and Henson, J. and Love, F. and Davis, W.R. and Franzon, P.D. and Bucher, M. and Basavarajaiah, S. and Julie Oh and Jenkal, R.},
|
|
@INPROCEEDINGS{4231502,
|
|
author={J. E. Stine and others},
|
|
booktitle=MSE,
|
|
title={{FreePDK}: An Open-Source Variation-Aware Design Kit},
|
|
year={2007},
|
|
pages={173-174},
|
|
doi={10.1109/MSE.2007.44},
|
|
month={June}
|
|
} |