mirror of https://github.com/VLSIDA/OpenRAM.git
94 lines
4.9 KiB
TeX
94 lines
4.9 KiB
TeX
\section{Background}
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\label{sec:background}
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% brief origin/background of memory compilers
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% Existence of memory compilers from the beginning
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Memory compilers have been used in Electronic Design Automation (EDA)
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design flows to reduce the design
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time long before contemporary
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compilers~\cite{broderson:sicompiler,johannsen:blocks}.
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However, these compilers were generally not portable as they were
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nothing more
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than quick scripts to aid designers. Porting to a new technology
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essentially required rewriting the scripts. However, the increase in
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design productivity when porting designs between technologies has led to
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more research on memory array
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compilers~\cite{cabe:flexible,huang:array,poechmueller:array,Xu:2007}.
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% Reason why compilers evolved to today's current version
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As technology entered the Deep Sub-Micron (DSM) era, memory designs
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became one of the most challenging parts of circuit design
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due to decreasing static noise margins (SNM), increasing fabrication
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variability, and increasing leakage power consumption.
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This increased the complexity of memory compilers dramatically as they had to
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adapt to the ever-changing technologies. Simultaneously, design
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methodologies shifted from silicon compilers to standard cell place
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and route methods which required large optimized libraries. During
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this time, industry began using third-party suppliers of standard cell
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libraries and memory compilers that allowed their reuse to amortize
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development costs. These next-generation memory compilers provided
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silicon-verification that allowed designers to focus on their new
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design contribution rather than time-consuming tasks such as memory
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generation.
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% Commercial industry memory compilers' description and cost
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Contemporary memory compilers have been widely used by industry, but
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the internal operation is typically hidden. Several prominent
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companies and foundries have provided memory compilers to their
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customers. These memory compilers usually allow customers to view
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front-end simulation, timing/power values, and pin locations after a
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license agreement is signed. Back-end features such as layout are
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normally supplied directly to the fab and are only given to the user
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for a licensing fee.
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% Examples of commercial compilers' drawbacks
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Specifically, Global Foundries offers front-end PDKs for free, but not
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back-end detailed views~\cite{globalfoundries:2015}. Faraday
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Technologies provides a \enquote{black box} design kit where users do
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not know the details of the internal memory
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design~\cite{faraday:2015}. Dolphin Technology offers closed-source
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compilers which can create RAMs, ROMs, and CAMs for a variety of
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technologies~\cite{dolphin:2015}. The majority of these commercial
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compilers do not allow the customer to alter the base design, are
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restricted by the company's license, and usually require a fee. This
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makes them virtually unavailable and not useful for many academic
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research projects.
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% Describe the problem (no free open-source that is widely distributed)
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In addition to memory compilers provided by industry, various research
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groups have released scripts to generate memories. However, these
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designs are not silicon verified and are usually only composed of
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simple structures. For example, FabMem is able to
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create small arrays, but it is highly dependent on the Cadence design
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tools~\cite{fabmem:2010}. The scripts do not provide any characterization capability
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and cannot easily integrate with commercial place and route tools.
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% Industry's attempt to provide academia a memory compiler
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Another recent, promising solution for academia is the Synopsys
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Generic Memory Compiler (GMC)~\cite{Goldman:2014}. The software is
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provided with sample generic libraries such as Synopsys' $32$/$28$nm and
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$90$nm abstract technologies and can generate the entire SRAM for these
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technologies. The GMC generates GDSII layout data, SPICE netlists,
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Verilog and VHDL models, timing/power libraries, and DRC/LVS
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verification reports. GMC, however, is not recommended for
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fabrication since the technologies it supports are not real. Its sole
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purpose is to aid students in VLSI courses to learn about using
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memories in design flows.
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% Academia's' attempts at a memory compiler
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There have been multiple attempts by academia to implement a memory
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compiler that is not restricted: the Institute of
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Microelectronics' SRAM IP Compiler~\cite{Xu:2007}, School of
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Electronic Science and Engineering at Southeast University's Memory IP
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Compiler~\cite{Chen:2012}, and Tsinghua University's Low Power SRAM
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Compiler~\cite{Wu:2010}. These are all methodologies and design flows
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for a memory compiler, but there are no public releases.
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% State what we are looking for in academia. -- duplicate from introduction
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%% With all these attempts, there still isn't a complete solution for
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%% academia's research needs. Researchers need a memory compiler that is
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%% open-source, platform- and tool-portable, technology independent, and
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%% can generate fabricable memory designs.
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