mirror of https://github.com/VLSIDA/OpenRAM.git
120 lines
4.2 KiB
Python
120 lines
4.2 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2022 Regents of the University of California
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# All rights reserved.
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#
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from tech import drc
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import debug
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from base import design
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import math
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from sram_factory import factory
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from base import vector
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from globals import OPTS
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from tech import cell_properties
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from tech import layer_properties as layer_props
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class column_decoder(design):
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"""
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Create the column mux decoder.
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"""
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def __init__(self, name, col_addr_size):
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super().__init__(name)
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self.col_addr_size = col_addr_size
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self.num_inputs = col_addr_size
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self.num_outputs = pow(2, col_addr_size)
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debug.info(2,
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"create column decoder of {0} inputs and {1} outputs".format(self.num_inputs,
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self.num_outputs))
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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self.DRC_LVS()
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def create_netlist(self):
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self.add_pins()
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self.add_modules()
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self.create_instances()
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def create_instances(self):
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self.column_decoder_inst = self.add_inst(name="column_decoder",
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mod=self.column_decoder)
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self.connect_inst(self.pins)
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def create_layout(self):
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self.column_decoder_inst.place(vector(0,0))
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self.width = self.column_decoder_inst.width
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self.height = self.column_decoder_inst.height
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self.route_layout()
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def add_pins(self):
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""" Add the module pins """
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for i in range(self.num_inputs):
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self.add_pin("in_{0}".format(i), "INPUT")
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for j in range(self.num_outputs):
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self.add_pin("out_{0}".format(j), "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def route_layout_pins(self):
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""" Add the pins. """
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if self.col_addr_size == 1:
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self.copy_layout_pin(self.column_decoder_inst, "A", "in_0")
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self.copy_layout_pin(self.column_decoder_inst, "Zb", "out_0")
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self.copy_layout_pin(self.column_decoder_inst, "Z", "out_1")
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elif self.col_addr_size > 1:
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for i in range(self.num_inputs):
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self.copy_layout_pin(self.column_decoder_inst, "in_{0}".format(i))
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for i in range(self.num_outputs):
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self.copy_layout_pin(self.column_decoder_inst, "out_{0}".format(i))
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def route_layout(self):
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""" Create routing among the modules """
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self.route_layout_pins()
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self.route_supplies()
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def route_supplies(self):
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""" Propagate all vdd/gnd pins up to this level for all modules """
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if self.col_addr_size == 1:
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self.copy_layout_pin(self.column_decoder_inst, "vdd")
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self.copy_layout_pin(self.column_decoder_inst, "gnd")
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else:
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self.route_vertical_pins("vdd", self.insts, xside="rx",)
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self.route_vertical_pins("gnd", self.insts, xside="lx",)
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def add_modules(self):
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self.dff =factory.create(module_type="dff")
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if self.col_addr_size == 1:
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self.column_decoder = factory.create(module_type="pinvbuf",
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height=self.dff.height)
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elif self.col_addr_size == 2:
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self.column_decoder = factory.create(module_type="hierarchical_predecode2x4",
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column_decoder=True,
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height=self.dff.height)
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elif self.col_addr_size == 3:
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self.column_decoder = factory.create(module_type="hierarchical_predecode3x8",
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column_decoder=True,
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height=self.dff.height)
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elif self.col_addr_size == 4:
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self.column_decoder = factory.create(module_type="hierarchical_predecode4x16",
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column_decoder=True,
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height=self.dff.height)
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else:
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# No error checking before?
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debug.error("Invalid column decoder?", -1)
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