mirror of https://github.com/VLSIDA/OpenRAM.git
5474 lines
258 KiB
Plaintext
5474 lines
258 KiB
Plaintext
VERSION 5.4 ;
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NAMESCASESENSITIVE ON ;
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BUSBITCHARS "[]" ;
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DIVIDERCHAR "/" ;
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UNITS
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DATABASE MICRONS 1000 ;
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END UNITS
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SITE MacroSite
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CLASS Core ;
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SIZE 305400.0 by 440700.0 ;
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END MacroSite
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MACRO sram_2_16_1_scn3me_subm
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CLASS BLOCK ;
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SIZE 305400.0 BY 440700.0 ;
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SYMMETRY X Y R90 ;
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SITE MacroSite ;
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PIN DATA[0]
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DIRECTION INOUT ;
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PORT
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LAYER metal2 ;
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RECT 180000.0 0.0 180900.0 1800.0 ;
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END
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END DATA[0]
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PIN DATA[1]
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DIRECTION INOUT ;
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PORT
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LAYER metal2 ;
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RECT 190200.0 0.0 191100.0 1800.0 ;
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END
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END DATA[1]
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PIN ADDR[0]
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DIRECTION INPUT ;
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PORT
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LAYER metal3 ;
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RECT 52800.0 77700.0 60000.0 79200.0 ;
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END
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END ADDR[0]
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PIN ADDR[1]
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DIRECTION INPUT ;
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PORT
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LAYER metal3 ;
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RECT 52800.0 67500.0 60000.0 69000.0 ;
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END
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END ADDR[1]
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PIN ADDR[2]
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DIRECTION INPUT ;
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PORT
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LAYER metal3 ;
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RECT 52800.0 57300.0 60000.0 58800.0 ;
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END
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END ADDR[2]
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PIN ADDR[3]
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DIRECTION INPUT ;
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PORT
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LAYER metal3 ;
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RECT 52800.0 47100.0 60000.0 48600.0 ;
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END
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END ADDR[3]
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PIN CSb
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DIRECTION INPUT ;
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PORT
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LAYER metal3 ;
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RECT 14400.0 203400.0 16200.0 205200.0 ;
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END
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END CSb
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PIN WEb
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DIRECTION INPUT ;
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PORT
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LAYER metal3 ;
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RECT 24600.0 203400.0 26400.0 205200.0 ;
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END
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END WEb
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PIN OEb
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DIRECTION INPUT ;
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PORT
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LAYER metal3 ;
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RECT 4200.0 203400.0 6000.0 205200.0 ;
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END
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END OEb
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PIN clk
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DIRECTION INPUT ;
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PORT
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LAYER metal1 ;
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RECT 42600.0 202500.0 43800.0 206100.0 ;
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END
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END clk
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PIN vdd
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DIRECTION INOUT ;
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USE POWER ;
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SHAPE ABUTMENT ;
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PORT
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LAYER metal1 ;
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RECT 198600.0 0.0 203100.0 440700.0 ;
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LAYER metal1 ;
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RECT 52800.0 0.0 57300.0 440700.0 ;
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END
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END vdd
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PIN gnd
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DIRECTION INOUT ;
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USE GROUND ;
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SHAPE ABUTMENT ;
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PORT
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LAYER metal2 ;
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RECT 148050.0 0.0 152550.0 440700.0 ;
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END
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END gnd
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OBS
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END
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END sram_2_16_1_scn3me_subm
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END LIBRARY
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