mirror of https://github.com/VLSIDA/OpenRAM.git
33 lines
1.1 KiB
Python
33 lines
1.1 KiB
Python
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California
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# All rights reserved.
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#
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from openram import debug
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from openram.modules import bitcell_base
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from openram.tech import cell_properties as props
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class sky130_dummy_bitcell(bitcell_base):
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"""
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A single bit cell (6T, 8T, etc.) This module implements the
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single memory cell used in the design. It is a hand-made cell, so
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the layout and netlist should be available in the technology
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library.
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"""
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def __init__(self, version, name=""):
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# Ignore the name argument
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if version == "opt1":
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cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1_dummy"
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elif version == "opt1a":
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cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1a_dummy"
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super().__init__(name, cell_name, prop=props.bitcell_1port)
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debug.info(2, "Create dummy bitcell")
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def build_graph(self, graph, inst_name, port_nets):
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""" Adds edges based on inputs/outputs. Overrides base class function. """
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pass
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