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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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d60986e5909ec496d995a6c8e13944fa0f35a7fc
OpenRAM/compiler/router
T
History
Matt Guthaus d855d4f1a6 Moving wide metal spacing to routing grid level
2018-10-15 09:59:16 -07:00
..
tests
Merge multiport
2018-10-08 11:45:50 -07:00
direction.py
Routing and connecting rails with vias done.
2018-09-07 14:46:58 -07:00
grid_cell.py
Supply router working except:
2018-09-18 12:57:39 -07:00
grid_path.py
Rewrote pin enclosure code to better address off grid pins.
2018-10-10 15:15:58 -07:00
grid.py
Cleanup of router.
2018-10-04 14:04:29 -07:00
router.py
Moving wide metal spacing to routing grid level
2018-10-15 09:59:16 -07:00
signal_grid.py
Rewrote pin enclosure code to better address off grid pins.
2018-10-10 15:15:58 -07:00
signal_router.py
Cleanup of router.
2018-10-04 14:04:29 -07:00
supply_grid.py
Supply router working except:
2018-09-18 12:57:39 -07:00
supply_router.py
Moving wide metal spacing to routing grid level
2018-10-15 09:59:16 -07:00
vector3d.py
DRC clean supply grid routing on control logic.
2018-09-20 16:00:13 -07:00
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