mirror of https://github.com/VLSIDA/OpenRAM.git
612 lines
23 KiB
Python
612 lines
23 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
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# All rights reserved.
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#
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from openram import debug
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from openram.base.vector import vector
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from openram.base.vector3d import vector3d
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from openram.gdsMill import gdsMill
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from openram.tech import GDS
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from openram.tech import drc
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from openram.tech import layer as tech_layer
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from openram import OPTS
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from .router_tech import router_tech
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from .graph import graph
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from .graph_shape import graph_shape
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from .graph_utils import snap
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class graph_router(router_tech):
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"""
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This is the router class that uses the Hanan grid method to route pins using
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a graph.
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"""
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def __init__(self, layers, design, bbox=None, pin_type=None):
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# `router_tech` contains tech constants for the router
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router_tech.__init__(self, layers, route_track_width=1)
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# Layers that can be used for routing
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self.layers = layers
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# This is the `hierarchy_layout` object
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self.design = design
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# Side supply pin type
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# (can be "top", "bottom", "right", "left", and "ring")
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self.pin_type = pin_type
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# Temporary GDSII file name to find pins and blockages
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self.gds_filename = OPTS.openram_temp + "temp.gds"
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# Dictionary for vdd and gnd pins
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self.pins = {}
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# Set of all the pins
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self.all_pins = set()
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# This is all the blockages including the pins. The graph class handles
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# pins as blockages while considering their routability
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self.blockages = []
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# This is all the vias between routing layers
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self.vias = []
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# New pins are the side supply pins
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self.new_pins = {}
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# Fake pins are imaginary pins on the side supply pins to route other
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# pins to them
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self.fake_pins = []
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# Set the offset here
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self.offset = snap(self.track_wire / 2)
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def route(self, vdd_name="vdd", gnd_name="gnd"):
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""" Route the given pins in the given order. """
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debug.info(1, "Running router for {} and {}...".format(vdd_name, gnd_name))
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# Save pin names
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self.vdd_name = vdd_name
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self.gnd_name = gnd_name
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# Prepare gdsMill to find pins and blockages
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self.prepare_gds_reader()
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# Find pins to be routed
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self.find_pins(vdd_name)
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self.find_pins(gnd_name)
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# Find blockages and vias
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self.find_blockages()
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self.find_vias()
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# Convert blockages and vias if they overlap a pin
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self.convert_vias()
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self.convert_blockages()
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# Add side pins
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self.calculate_ring_bbox()
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if self.pin_type in ["top", "bottom", "right", "left"]:
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self.add_side_pin(vdd_name)
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self.add_side_pin(gnd_name)
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elif self.pin_type == "ring":
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self.add_ring_pin(vdd_name)
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self.add_ring_pin(gnd_name)
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else:
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debug.warning("Side supply pins aren't created.")
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# Add vdd and gnd pins as blockages as well
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# NOTE: This is done to make vdd and gnd pins DRC-safe
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for pin in self.all_pins:
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self.blockages.append(self.inflate_shape(pin, is_pin=True))
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# Route vdd and gnd
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for pin_name in [vdd_name, gnd_name]:
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pins = self.pins[pin_name]
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# Route closest pins according to the minimum spanning tree
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for source, target in self.get_mst_pairs(list(pins)):
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# This is the routing region scale
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scale = 1
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while True:
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# Create the graph
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g = graph(self)
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region = g.create_graph(source, target, scale)
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# Find the shortest path from source to target
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path = g.find_shortest_path()
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# If there is no path found, exponentially try again with a
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# larger routing region
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if path is None:
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rll, rur = region
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bll, bur = self.ring_bbox
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# Stop scaling the region and throw an error
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if rll.x < bll.x and rll.y < bll.y and \
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rur.x > bur.x and rur.y > bur.y:
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self.write_debug_gds(gds_name="{}error.gds".format(OPTS.openram_temp), g=g, source=source, target=target)
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debug.error("Couldn't route from {} to {}.".format(source, target), -1)
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# Exponentially scale the region
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scale *= 2
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debug.info(0, "Retry routing in larger routing region with scale {}".format(scale))
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continue
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# Create the path shapes on layout
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self.add_path(path)
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# Find the recently added shapes
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self.prepare_gds_reader()
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self.find_blockages(pin_name)
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self.find_vias()
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break
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def prepare_gds_reader(self):
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""" Write the current layout to a temporary file to read the layout. """
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self.design.gds_write(self.gds_filename)
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self.layout = gdsMill.VlsiLayout(units=GDS["unit"])
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self.reader = gdsMill.Gds2reader(self.layout)
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self.reader.loadFromFile(self.gds_filename)
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def merge_shapes(self, merger, shape_list):
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"""
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Merge shapes in the list into the merger if they are contained or
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aligned by the merger.
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"""
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merger_core = merger.get_core()
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for shape in list(shape_list):
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shape_core = shape.get_core()
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# If merger contains the shape, remove it from the list
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if merger_core.contains(shape_core):
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shape_list.remove(shape)
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# If the merger aligns with the shape, expand the merger and remove
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# the shape from the list
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elif merger_core.aligns(shape_core):
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merger.bbox([shape])
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merger_core.bbox([shape_core])
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shape_list.remove(shape)
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def find_pins(self, pin_name):
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""" Find the pins with the given name. """
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debug.info(2, "Finding all pins for {}".format(pin_name))
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shape_list = self.layout.getAllPinShapes(str(pin_name))
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pin_set = set()
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for shape in shape_list:
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layer, boundary = shape
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# gdsMill boundaries are in (left, bottom, right, top) order
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ll = vector(boundary[0], boundary[1])
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ur = vector(boundary[2], boundary[3])
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rect = [ll, ur]
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new_pin = graph_shape(pin_name, rect, layer)
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# Skip this pin if it's contained by another pin of the same type
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if new_pin.core_contained_by_any(pin_set):
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continue
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# Merge previous pins into this one if possible
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self.merge_shapes(new_pin, pin_set)
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pin_set.add(new_pin)
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# Add these pins to the 'pins' dict
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self.pins[pin_name] = pin_set
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self.all_pins.update(pin_set)
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def find_blockages(self, name="blockage"):
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""" Find all blockages in the routing layers. """
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debug.info(2, "Finding blockages...")
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for lpp in [self.vert_lpp, self.horiz_lpp]:
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shapes = self.layout.getAllShapes(lpp)
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for boundary in shapes:
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# gdsMill boundaries are in (left, bottom, right, top) order
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ll = vector(boundary[0], boundary[1])
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ur = vector(boundary[2], boundary[3])
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rect = [ll, ur]
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new_shape = graph_shape(name, rect, lpp)
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new_shape = self.inflate_shape(new_shape)
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# Skip this blockage if it's contained by a pin or an existing
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# blockage
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if new_shape.core_contained_by_any(self.all_pins) or \
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new_shape.core_contained_by_any(self.blockages):
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continue
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# Merge previous blockages into this one if possible
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self.merge_shapes(new_shape, self.blockages)
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self.blockages.append(new_shape)
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def find_vias(self):
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""" Find all vias in the routing layers. """
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debug.info(2, "Finding vias...")
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# Prepare lpp values here
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from openram.tech import layer
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via_lpp = layer[self.via_layer_name]
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valid_lpp = self.horiz_lpp
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shapes = self.layout.getAllShapes(via_lpp)
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for boundary in shapes:
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# gdsMill boundaries are in (left, bottom, right, top) order
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ll = vector(boundary[0], boundary[1])
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ur = vector(boundary[2], boundary[3])
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rect = [ll, ur]
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new_shape = graph_shape("via", rect, valid_lpp)
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# Skip this via if it's contained by an existing via blockage
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if new_shape.contained_by_any(self.vias):
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continue
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self.vias.append(self.inflate_shape(new_shape, is_via=True))
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def convert_vias(self):
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""" Convert vias that overlap a pin. """
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for via in self.vias:
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via_core = via.get_core()
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for pin in self.all_pins:
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pin_core = pin.get_core()
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via_core.lpp = pin_core.lpp
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# If the via overlaps a pin, change its name
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if via_core.overlaps(pin_core):
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via.rename(pin.name)
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break
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def convert_blockages(self):
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""" Convert blockages that overlap a pin. """
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# NOTE: You need to run `convert_vias()` before since a blockage may
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# be connected to a pin through a via.
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for blockage in self.blockages:
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blockage_core = blockage.get_core()
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for pin in self.all_pins:
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pin_core = pin.get_core()
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# If the blockage overlaps a pin, change its name
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if blockage_core.overlaps(pin_core):
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blockage.rename(pin.name)
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break
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else:
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for via in self.vias:
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# Skip if this via isn't connected to a pin
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if via.name == "via":
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continue
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via_core = via.get_core()
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via_core.lpp = blockage_core.lpp
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# If the blockage overlaps a pin via, change its name
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if blockage_core.overlaps(via_core):
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blockage.rename(via.name)
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break
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def inflate_shape(self, shape, is_pin=False, is_via=False):
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""" Inflate a given shape with spacing rules. """
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# Pins must keep their center lines away from any blockage to prevent
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# the nodes from being unconnected
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if is_pin:
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xdiff = self.layer_widths[0] - shape.width()
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ydiff = self.layer_widths[0] - shape.height()
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diff = max(xdiff, ydiff) / 2
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spacing = self.track_space + drc["grid"]
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if diff > 0:
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spacing += diff
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# Vias are inflated by the maximum spacing rule
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elif is_via:
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spacing = self.track_space
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# Blockages are inflated by their layer's corresponding spacing rule
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else:
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if self.get_zindex(shape.lpp) == 1:
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spacing = self.vert_layer_spacing
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else:
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spacing = self.horiz_layer_spacing
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# If the shape is wider than the supply wire width, its spacing can be
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# different
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wide = min(shape.width(), shape.height())
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if wide > self.layer_widths[0]:
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spacing = self.get_layer_space(self.get_zindex(shape.lpp), wide)
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return shape.inflated_pin(spacing=spacing,
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extra_spacing=self.offset)
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def calculate_ring_bbox(self, num_vias=3):
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""" Calculate the ring-safe bounding box of the layout. """
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ll, ur = self.design.get_bbox()
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# Calculate the "wideness" of a side supply pin
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wideness = self.track_wire * num_vias + self.track_space * (num_vias - 1)
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# Total wideness is used to find it any pin overlaps in this region. If
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# so, the bbox is shifted to prevent this overlap.
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total_wideness = wideness * 4
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for blockage in self.blockages:
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bll, bur = blockage.rect
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if self.get_zindex(blockage.lpp) == 1: # Vertical
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diff = ll.x + total_wideness - bll.x
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if diff > 0:
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ll = vector(ll.x - diff, ll.y)
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diff = ur.x - total_wideness - bur.x
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if diff < 0:
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ur = vector(ur.x - diff, ur.y)
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else: # Horizontal
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diff = ll.y + total_wideness - bll.y
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if diff > 0:
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ll = vector(ll.x, ll.y - diff)
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diff = ur.y - total_wideness - bur.y
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if diff < 0:
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ur = vector(ur.x, ur.y - diff)
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self.ring_bbox = [ll, ur]
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def add_side_pin(self, pin_name, side, num_vias=3, num_fake_pins=4):
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""" Add supply pin to one side of the layout. """
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ll, ur = self.ring_bbox
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vertical = side in ["left", "right"]
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inner = pin_name == self.gnd_name
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# Calculate wires' wideness
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wideness = self.track_wire * num_vias + self.track_space * (num_vias - 1)
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# Calculate the offset for the inner ring
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if inner:
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margin = wideness * 2
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else:
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margin = 0
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# Calculate the lower left coordinate
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if side == "top":
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offset = vector(ll.x + margin, ur.y - wideness - margin)
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elif side == "bottom":
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offset = vector(ll.x + margin, ll.y + margin)
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elif side == "left":
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offset = vector(ll.x + margin, ll.y + margin)
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elif side == "right":
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offset = vector(ur.x - wideness - margin, ll.y + margin)
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# Calculate width and height
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shape = ur - ll
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if vertical:
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shape_width = wideness
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shape_height = shape.y
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else:
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shape_width = shape.x
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shape_height = wideness
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if inner:
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if vertical:
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shape_height -= margin * 2
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else:
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shape_width -= margin * 2
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# Add this new pin
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layer = self.get_layer(int(vertical))
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pin = self.design.add_layout_pin(text=pin_name,
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layer=layer,
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offset=offset,
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width=shape_width,
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height=shape_height)
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# Add fake pins on this new pin evenly
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fake_pins = []
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if vertical:
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space = (shape_height - (2 * wideness) - num_fake_pins * self.track_wire) / (num_fake_pins + 1)
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start_offset = vector(offset.x, offset.y + wideness)
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else:
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space = (shape_width - (2 * wideness) - num_fake_pins * self.track_wire) / (num_fake_pins + 1)
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start_offset = vector(offset.x + wideness, offset.y)
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for i in range(1, num_fake_pins + 1):
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if vertical:
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offset = vector(start_offset.x, start_offset.y + i * (space + self.track_wire))
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ll = vector(offset.x, offset.y - self.track_wire)
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ur = vector(offset.x + wideness, offset.y)
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else:
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offset = vector(start_offset.x + i * (space + self.track_wire), start_offset.y)
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ll = vector(offset.x - self.track_wire, offset.y)
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ur = vector(offset.x, offset.y + wideness)
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rect = [ll, ur]
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fake_pin = graph_shape(name=pin_name,
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rect=rect,
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layer_name_pp=layer)
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fake_pins.append(fake_pin)
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return pin, fake_pins
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def add_ring_pin(self, pin_name, num_vias=3, num_fake_pins=4):
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""" Add the supply ring to the layout. """
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# Add side pins
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new_pins = []
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for side in ["top", "bottom", "right", "left"]:
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new_shape, fake_pins = self.add_side_pin(pin_name, side, num_vias, num_fake_pins)
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ll, ur = new_shape.rect
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rect = [ll, ur]
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layer = self.get_layer(side in ["left", "right"])
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new_pin = graph_shape(name=pin_name,
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rect=rect,
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layer_name_pp=layer)
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new_pins.append(new_pin)
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self.pins[pin_name].update(fake_pins)
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self.fake_pins.extend(fake_pins)
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# Add vias to the corners
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shift = self.track_wire + self.track_space
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half_wide = self.track_wire / 2
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for i in range(4):
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ll, ur = new_pins[i].rect
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if i % 2:
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top_left = vector(ur.x - (num_vias - 1) * shift - half_wide, ll.y + (num_vias - 1) * shift + half_wide)
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else:
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top_left = vector(ll.x + half_wide, ur.y - half_wide)
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for j in range(num_vias):
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for k in range(num_vias):
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offset = vector(top_left.x + j * shift, top_left.y - k * shift)
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self.design.add_via_center(layers=self.layers,
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offset=offset)
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# Save side pins for routing
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self.new_pins[pin_name] = new_pins
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for pin in new_pins:
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self.blockages.append(self.inflate_shape(pin, is_pin=True))
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def get_mst_pairs(self, pins):
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"""
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Return the pin pairs from the minimum spanning tree in a graph that
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connects all pins together.
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"""
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pin_count = len(pins)
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# Create an adjacency matrix that connects all pins
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edges = [[0] * pin_count for i in range(pin_count)]
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for i in range(pin_count):
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for j in range(pin_count):
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# Skip if they're the same pin
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if i == j:
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continue
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# Skip if both pins are fake
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if pins[i] in self.fake_pins and pins[j] in self.fake_pins:
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continue
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edges[i][j] = pins[i].distance(pins[j])
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pin_connected = [False] * pin_count
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pin_connected[0] = True
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# Add the minimum cost edge in each iteration (Prim's)
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mst_pairs = []
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for i in range(pin_count - 1):
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min_cost = float("inf")
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s = 0
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t = 0
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# Iterate over already connected pins
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for m in range(pin_count):
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# Skip if not connected
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if not pin_connected[m]:
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continue
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# Iterate over this pin's neighbors
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for n in range(pin_count):
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# Skip if already connected or isn't a neighbor
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if pin_connected[n] or edges[m][n] == 0:
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continue
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# Choose this edge if it's better the the current one
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if edges[m][n] < min_cost:
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|
min_cost = edges[m][n]
|
|
s = m
|
|
t = n
|
|
pin_connected[t] = True
|
|
mst_pairs.append((pins[s], pins[t]))
|
|
|
|
return mst_pairs
|
|
|
|
|
|
def add_path(self, path):
|
|
""" Add the route path to the layout. """
|
|
|
|
nodes = self.prepare_path(path)
|
|
self.add_route(nodes)
|
|
|
|
|
|
def prepare_path(self, path):
|
|
"""
|
|
Remove unnecessary nodes on the path to reduce the number of shapes in
|
|
the layout.
|
|
"""
|
|
|
|
last_added = path[0]
|
|
nodes = [path[0]]
|
|
direction = path[0].get_direction(path[1])
|
|
candidate = path[1]
|
|
for i in range(2, len(path)):
|
|
node = path[i]
|
|
current_direction = node.get_direction(candidate)
|
|
# Skip the previous candidate since the current node follows the
|
|
# same direction
|
|
if direction == current_direction:
|
|
candidate = node
|
|
else:
|
|
last_added = candidate
|
|
nodes.append(candidate)
|
|
direction = current_direction
|
|
candidate = node
|
|
if candidate not in nodes:
|
|
nodes.append(candidate)
|
|
return nodes
|
|
|
|
|
|
def add_route(self, nodes):
|
|
"""
|
|
Custom `add_route` function since `hierarchy_layout.add_route` isn't
|
|
working for this router.
|
|
"""
|
|
|
|
for i in range(0, len(nodes) - 1):
|
|
start = nodes[i].center
|
|
end = nodes[i + 1].center
|
|
direction = nodes[i].get_direction(nodes[i + 1])
|
|
diff = start - end
|
|
offset = start.min(end)
|
|
offset = vector(offset.x - self.offset, offset.y - self.offset)
|
|
if direction == (1, 1): # Via
|
|
offset = vector(start.x, start.y)
|
|
self.design.add_via_center(layers=self.layers,
|
|
offset=offset)
|
|
else: # Wire
|
|
self.design.add_rect(layer=self.get_layer(start.z),
|
|
offset=offset,
|
|
width=abs(diff.x) + self.track_wire,
|
|
height=abs(diff.y) + self.track_wire)
|
|
|
|
|
|
def get_new_pins(self, name):
|
|
""" Return the new supply pins added by this router. """
|
|
|
|
return self.new_pins[name]
|
|
|
|
|
|
def write_debug_gds(self, gds_name="debug_route.gds", g=None, source=None, target=None):
|
|
""" Write the debug GDSII file for the router. """
|
|
|
|
self.add_router_info(g, source, target)
|
|
self.design.gds_write(gds_name)
|
|
self.del_router_info()
|
|
|
|
|
|
def add_router_info(self, g=None, source=None, target=None):
|
|
"""
|
|
Add debug information to the text layer about the graph and router.
|
|
"""
|
|
|
|
# Display the inflated blockage
|
|
if g:
|
|
for blockage in self.blockages:
|
|
if blockage in g.graph_blockages:
|
|
self.add_object_info(blockage, "blockage{}++[{}]".format(self.get_zindex(blockage.lpp), blockage.name))
|
|
else:
|
|
self.add_object_info(blockage, "blockage{}[{}]".format(self.get_zindex(blockage.lpp), blockage.name))
|
|
for node in g.nodes:
|
|
offset = (node.center.x, node.center.y)
|
|
self.design.add_label(text="n{}".format(node.center.z),
|
|
layer="text",
|
|
offset=offset)
|
|
#debug.info(0, "Neighbors of {}".format(node.center))
|
|
#for neighbor in node.neighbors:
|
|
# debug.info(0, " {}".format(neighbor.center))
|
|
else:
|
|
for blockage in self.blockages:
|
|
self.add_object_info(blockage, "blockage{}".format(self.get_zindex(blockage.lpp)))
|
|
for pin in self.fake_pins:
|
|
self.add_object_info(pin, "fake")
|
|
if source:
|
|
self.add_object_info(source, "source")
|
|
if target:
|
|
self.add_object_info(target, "target")
|
|
|
|
|
|
def del_router_info(self):
|
|
""" Delete router information from the text layer. """
|
|
|
|
lpp = tech_layer["text"]
|
|
self.design.objs = [x for x in self.design.objs if x.lpp != lpp]
|
|
|
|
|
|
def add_object_info(self, obj, label):
|
|
""" Add debug information to the text layer about an object. """
|
|
|
|
ll, ur = obj.rect
|
|
self.design.add_rect(layer="text",
|
|
offset=ll,
|
|
width=ur.x - ll.x,
|
|
height=ur.y - ll.y)
|
|
self.design.add_label(text=label,
|
|
layer="text",
|
|
offset=ll)
|