mirror of https://github.com/VLSIDA/OpenRAM.git
105 lines
4.4 KiB
Python
105 lines
4.4 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from tech import drc,layer
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from contact import contact
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from pin_group import pin_group
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from vector import vector
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import debug
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import math
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class router_tech:
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"""
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This is a class to hold the router tech constants.
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"""
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def __init__(self, layers, rail_track_width):
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"""
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Allows us to change the layers that we are routing on. First layer
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is always horizontal, middle is via, and last is always
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vertical.
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"""
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self.layers = layers
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self.rail_track_width = rail_track_width
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if len(self.layers)==1:
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self.horiz_layer_name = self.vert_layer_name = self.layers[0]
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self.horiz_layer_number = self.vert_layer_number = layer[self.layers[0]]
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(self.vert_layer_minwidth, self.vert_layer_spacing) = self.get_supply_layer_width_space(1)
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(self.horiz_layer_minwidth, self.horiz_layer_spacing) = self.get_supply_layer_width_space(0)
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self.horiz_track_width = self.horiz_layer_minwidth + self.horiz_layer_spacing
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self.vert_track_width = self.vert_layer_minwidth + self.vert_layer_spacing
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else:
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(self.horiz_layer_name, self.via_layer_name, self.vert_layer_name) = self.layers
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via_connect = contact(self.layers, (1, 1))
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max_via_size = max(via_connect.width,via_connect.height)
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self.horiz_layer_number = layer[self.horiz_layer_name]
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self.vert_layer_number = layer[self.vert_layer_name]
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(self.vert_layer_minwidth, self.vert_layer_spacing) = self.get_supply_layer_width_space(1)
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(self.horiz_layer_minwidth, self.horiz_layer_spacing) = self.get_supply_layer_width_space(0)
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# For supplies, we will make the wire wider than the vias
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self.vert_layer_minwidth = max(self.vert_layer_minwidth, max_via_size)
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self.horiz_layer_minwidth = max(self.horiz_layer_minwidth, max_via_size)
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self.horiz_track_width = self.horiz_layer_minwidth + self.horiz_layer_spacing
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self.vert_track_width = self.vert_layer_minwidth + self.vert_layer_spacing
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# We'll keep horizontal and vertical tracks the same for simplicity.
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self.track_width = max(self.horiz_track_width,self.vert_track_width)
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debug.info(1,"Track width: {:.3f}".format(self.track_width))
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self.track_space = max(self.horiz_layer_spacing,self.vert_layer_spacing)
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debug.info(1,"Track space: {:.3f}".format(self.track_space))
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self.track_wire = self.track_width - self.track_space
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debug.info(1,"Track wire width: {:.3f}".format(self.track_wire))
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self.track_widths = vector([self.track_width] * 2)
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self.track_factor = vector([1/self.track_width] * 2)
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debug.info(2,"Track factor: {}".format(self.track_factor))
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# When we actually create the routes, make them the width of the track (minus 1/2 spacing on each side)
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self.layer_widths = [self.track_wire, 1, self.track_wire]
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def get_zindex(self,layer_num):
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if layer_num==self.horiz_layer_number:
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return 0
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else:
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return 1
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def get_layer(self, zindex):
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if zindex==1:
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return self.vert_layer_name
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elif zindex==0:
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return self.horiz_layer_name
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else:
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debug.error("Invalid zindex {}".format(zindex),-1)
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def get_supply_layer_width_space(self, zindex):
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"""
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These are the width and spacing of a supply layer given a supply rail
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of the given number of min wire widths.
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"""
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if zindex==1:
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layer_name = self.vert_layer_name
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elif zindex==0:
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layer_name = self.horiz_layer_name
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else:
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debug.error("Invalid zindex for track", -1)
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min_wire_width = drc("minwidth_{0}".format(layer_name), 0, math.inf)
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min_width = drc("minwidth_{0}".format(layer_name), self.rail_track_width*min_wire_width, math.inf)
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min_spacing = drc(str(layer_name)+"_to_"+str(layer_name), self.rail_track_width*min_wire_width, math.inf)
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return (min_width,min_spacing)
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