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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity
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d08181455c436aef8996a86da24fcaea5996fbe6
OpenRAM/compiler/base
T
History
Hunter Nichols d08181455c Added multiport bitcell support for storage node checks
2019-05-20 22:50:03 -07:00
..
contact.py
Update copyright to correct years.
2019-05-06 06:50:15 -07:00
design.py
Merged with dev
2019-05-15 18:48:00 -07:00
geometry.py
Update copyright to correct years.
2019-05-06 06:50:15 -07:00
graph_util.py
Added graph to characterizer to get net names and perform s_en checks. Graph not working with column mux.
2019-05-14 14:44:49 -07:00
hierarchy_design.py
Merged with dev
2019-05-15 18:48:00 -07:00
hierarchy_layout.py
Update copyright to correct years.
2019-05-06 06:50:15 -07:00
hierarchy_spice.py
Added multiport bitcell support for storage node checks
2019-05-20 22:50:03 -07:00
lef.py
Update copyright to correct years.
2019-05-06 06:50:15 -07:00
pin_layout.py
Update copyright to correct years.
2019-05-06 06:50:15 -07:00
route.py
Update copyright to correct years.
2019-05-06 06:50:15 -07:00
utils.py
Update copyright to correct years.
2019-05-06 06:50:15 -07:00
vector.py
Update copyright to correct years.
2019-05-06 06:50:15 -07:00
verilog.py
Update copyright to correct years.
2019-05-06 06:50:15 -07:00
wire_path.py
Update copyright to correct years.
2019-05-06 06:50:15 -07:00
wire.py
Update copyright to correct years.
2019-05-06 06:50:15 -07:00
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