OpenRAM/compiler/router
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches.
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
2020-05-10 11:32:45 -07:00
..
tests
direction.py
grid.py
grid_cell.py
grid_path.py
grid_utils.py
pin_group.py
router.py
router_tech.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
signal_grid.py
signal_router.py
supply_grid.py
supply_grid_router.py Changes to allow decoder height to be a 2x multiple of bitcell height. 2020-05-10 06:56:22 -07:00
supply_tree_router.py
vector3d.py vector: Implement hash cache for vector3d and vector 2020-01-03 12:16:10 +01:00