mirror of https://github.com/VLSIDA/OpenRAM.git
78 lines
2.7 KiB
Python
78 lines
2.7 KiB
Python
import design
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import debug
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from tech import drc
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from vector import vector
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from precharge import precharge
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class precharge_array(design.design):
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"""
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Dynamically generated precharge array of all bitlines. Cols is number
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of bit line columns, height is the height of the bit-cell array.
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"""
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def __init__(self, columns, ptx_width, beta=2):
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design.design.__init__(self, "precharge_array")
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debug.info(1, "Creating {0}".format(self.name))
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self.columns = columns
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self.ptx_width = ptx_width
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self.beta = beta
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self.pc_cell = precharge(name="precharge_cell",
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ptx_width=self.ptx_width,
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beta=self.beta)
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self.add_mod(self.pc_cell)
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self.width = self.columns * self.pc_cell.width
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self.height = self.pc_cell.height
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self.add_pins()
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self.create_layout()
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self.DRC_LVS()
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def add_pins(self):
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"""Adds pins for spice file"""
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for i in range(self.columns):
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self.add_pin("bl[{0}]".format(i))
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self.add_pin("br[{0}]".format(i))
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self.add_pin("clk")
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self.add_pin("vdd")
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def create_layout(self):
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self.add_insts()
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=self.pc_cell.get_pin("vdd").ll(),
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width=self.width,
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height=drc["minwidth_metal1"])
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self.add_layout_pin(text="clk",
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layer="metal1",
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offset=self.pc_cell.get_pin("clk").ll(),
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width=self.width,
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height=drc["minwidth_metal1"])
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#self.offset_all_coordinates()
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def add_insts(self):
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"""Creates a precharge array by horizontally tiling the precharge cell"""
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self.pc_cell_positions = []
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for i in range(self.columns):
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name = "pre_column_{0}".format(i)
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offset = vector(self.pc_cell.width * i, 0)
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self.pc_cell_positions.append(offset)
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self.add_inst(name=name,
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mod=self.pc_cell,
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offset=offset)
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self.add_layout_pin(text="bl[{0}]".format(i),
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layer="metal2",
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offset=offset+ self.pc_cell.get_pin("BL").ll().scale(1,0))
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self.add_layout_pin(text="br[{0}]".format(i),
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layer="metal2",
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offset=offset+ self.pc_cell.get_pin("BR").ll().scale(1,0))
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self.connect_inst(["bl[{0}]".format(i), "br[{0}]".format(i),
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"clk", "vdd"])
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