mirror of https://github.com/VLSIDA/OpenRAM.git
203 lines
6.9 KiB
Python
203 lines
6.9 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from math import ceil
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from openram.base import geometry
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from openram.base import design
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from openram.sram_factory import factory
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from openram.base import vector
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from openram.tech import layer, drc
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class rom_precharge_array(design):
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"""
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An array of inverters to create the inverted address lines for the rom decoder
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"""
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def __init__(self, cols, pmos_size=None, name="", route_layer="li", strap_spacing=None):
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self.cols = cols
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self.route_layer = route_layer
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if name=="":
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name = "rom_inv_array_{0}".format(cols)
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# if pmos_size == None:
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# self.pmos_size = dff.height * 0.5
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# else:
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# self.pmos_size = inv_size
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if strap_spacing != None:
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self.strap_spacing = strap_spacing
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else:
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self.strap_spacing = 0
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if "li" in layer:
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self.inv_layer = "li"
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else:
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self.inv_layer = "m1"
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if strap_spacing != 0:
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self.num_straps = ceil(self.cols / self.strap_spacing)
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self.array_col_size = self.cols + self.num_straps
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else:
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self.num_straps = 0
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self.array_col_size = self.cols
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super().__init__(name)
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self.create_netlist()
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self.create_layout()
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def create_netlist(self):
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self.create_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.width = self.cols * self.pmos.width + self.num_straps * self.poly_tap.width
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self.height = self.pmos.width
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self.place_instances()
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self.create_layout_pins()
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self.add_well_tap()
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self.route_supply()
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self.extend_implant()
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self.add_boundary()
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def add_boundary(self):
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self.translate_all(self.well_ll)
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ur = self.find_highest_coords()
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ur = vector(ur.x, ur.y - self.well_ll.y)
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super().add_boundary(vector(0, 0), ur)
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self.width = self.cols * self.pmos.width + self.num_straps * self.poly_tap.width
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self.height = ur.y
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def create_modules(self):
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self.pmos = factory.create(module_type="rom_precharge_cell", module_name="precharge_cell", route_layer=self.route_layer)
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# For layout constants
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self.dummy = factory.create(module_type="rom_base_cell")
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self.poly_tap = factory.create(module_type="rom_poly_tap", strap_length=self.strap_spacing, tx_type="pmos")
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def add_pins(self):
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for col in range(self.cols):
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self.add_pin("pre_bl{0}_out".format(col), "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gate", "INPUT")
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def create_instances(self):
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self.array_insts = []
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self.pmos_insts = []
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self.tap_insts = []
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for col in range(self.cols):
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if col % self.strap_spacing == 0:
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name = "tap_c{}".format(col)
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tap = self.add_inst(name=name, mod=self.poly_tap)
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self.array_insts.append(tap)
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self.tap_insts.append(tap)
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self.connect_inst([])
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name = "Xpmos_c{0}".format(col)
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pmos = self.add_inst(name=name, mod=self.pmos)
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self.array_insts.append(pmos)
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self.pmos_insts.append(pmos)
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bl = "pre_bl{0}_out".format(col)
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self.connect_inst(["vdd", "gate", bl, "vdd"])
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print(self.array_insts)
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def place_instances(self):
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self.add_label("ZERO", self.route_layer)
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self.array_pos = []
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strap_num = 0
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cell_y = 0
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# columns are bit lines4
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cell_x = 0
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print("starting array place")
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for col in range(self.cols):
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if col % self.strap_spacing == 0 :
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self.tap_insts[strap_num].place(vector(cell_x, cell_y))
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self.add_label("debug", "li", vector(cell_x, cell_y))
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cell_x += self.poly_tap.width
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strap_num += 1
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self.pmos_insts[col].place(vector(cell_x, cell_y))
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self.add_label("debug", "li", vector(cell_x, cell_y))
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cell_x += self.pmos.width
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def create_layout_pins(self):
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self.copy_layout_pin(self.tap_insts[0], "via", "gate")
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for col in range(self.cols):
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source_pin = self.pmos_insts[col].get_pin("D")
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bl = "pre_bl{0}_out".format(col)
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self.add_layout_pin_rect_center(bl, self.route_layer, source_pin.center())
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def extend_implant(self):
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layer = "nwell"
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# center of source contact minus radius of the well generated by the contact gives the lowermost well position
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contact_well_by = self.pmos.pmos.source_contacts[0].cx() - self.pmos.pmos.source_contacts[0].mod.well_width * 0.5
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ptx_well_by = 0.5 * self.pmos.pmos.active_width - 0.5 * self.pmos.pmos.well_width
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well_extend = ptx_well_by - contact_well_by
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self.well_ll = vector(0, min(contact_well_by, ptx_well_by))
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height = self.pmos.pmos.active_width + 2 * self.well_enclose_active
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self.add_rect(layer, self.well_ll, self.width + well_extend, height + 2 * well_extend)
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def add_well_tap(self):
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layer_stack = self.active_stack
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contact_x = self.pmos_insts[self.cols - 1].rx() + self.active_space
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contact_offset = vector(contact_x, self.pmos.height * 0.5)
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self.nwell_contact = self.add_via_center(layers=layer_stack,
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offset=contact_offset,
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implant_type="n",
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well_type="n",
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directions=("V", "V"))
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def route_supply(self):
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start_pin = self.pmos_insts[0].get_pin("S").lx()
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end_pin = self.pmos_insts[-1].get_pin("S").rx()
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spacing = drc["{0}_to_{0}".format(self.route_layer)]
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start = vector(start_pin, -1.5*spacing)
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end = vector(end_pin, -1.5*spacing)
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self.vdd = self.add_layout_pin_segment_center("vdd", "m1", start, end)
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for i in range(self.cols):
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start = self.pmos_insts[i].get_pin("S").center()
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end = vector(start.x, self.vdd.cy())
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self.add_segment_center(self.route_layer, start, end)
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self.add_via_stack_center(end, self.route_layer, "m1")
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# connect nwell tap to vdd
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start = end
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end = vector(self.nwell_contact.cx(), start.y)
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self.add_segment_center(self.route_layer, start, end)
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start = end - vector(0, 0.5 * self.mcon_width)
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end = self.nwell_contact.center()
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self.add_segment_center(self.route_layer, start, end)
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