mirror of https://github.com/VLSIDA/OpenRAM.git
151 lines
5.7 KiB
Python
151 lines
5.7 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram.base import design
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from openram.base import vector
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from openram import OPTS
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from openram.sram_factory import factory
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from openram.tech import drc
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class rom_dummy_cell(design):
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def __init__(self, name="", cell_name=None, add_source_contact=False, add_drain_contact=False, route_layer="m1"):
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super().__init__(name, cell_name)
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self.route_layer = route_layer
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self.add_source_contact="li"
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self.add_drain_contact="li"
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self.create_netlist()
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self.create_layout()
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def create_netlist(self):
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#creates nmos for layout dimensions
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self.add_nmos()
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#set height and width such that the cell will tile perfectly by only ofsetting in the array by its width and height
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def create_layout(self):
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self.setup_drc_offsets()
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self.add_boundary()
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self.add_poly()
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self.add_metal()
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#self.add_label("0,0", self.route_layer)
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# Calculates offsets of cell width and height so that tiling of cells does not violate any drc rules
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def setup_drc_offsets(self):
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#nmos contact to gate distance
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self.contact_to_gate = 0.5 * (self.nmos.width - 2 * self.nmos.contact_width - self.nmos.poly_width - 2 * self.active_enclose_contact)
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#height offset to account for active-to-active spacing between adjacent bitlines
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self.poly_extend_active_spacing = abs( 2 * self.nmos.poly_extend_active - drc("active_to_active") )
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#contact to contact distance, minimum cell width before drc offsets
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self.base_width = self.nmos.width - 2 * self.active_enclose_contact - self.nmos.contact_width
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#width offset to account for active-to-active spacing between cells on the same bitline
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#this is calculated as a negative value
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self.cell_diffusion_offset = ((self.base_width - 2 * self.active_enclose_contact - self.nmos.contact_width) - drc("active_to_active")) * 0.5
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# width offset to account for poly-active spacing between base and dummy cells on the same bitline
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self.poly_active_offset = 0.5 * (self.base_width - 2 * self.cell_diffusion_offset - (self.poly_width + 2 * self.active_enclose_contact + self.nmos.contact_width)) - self.poly_to_active
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#so that the poly taps are far enough apart
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self.poly_tap_offset = (self.base_width - self.cell_diffusion_offset - self.poly_contact.width - self.poly_active_offset) - drc("poly_to_poly")
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def add_boundary(self):
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width = self.nmos.width + self.active_space
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#cell width with offsets applied, height becomes width when the cells are rotated
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# width = self.nmos.height + self.poly_extend_active_spacing + 2 * self.nmos.poly_extend_active
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# cell height with offsets applied, width becomes height when the cells are rotated, if the offsets are positive (greater than 0) they are not applied
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height = self.base_width - min(self.cell_diffusion_offset, 0) - min(self.poly_active_offset, 0) - min(self.poly_tap_offset, 0)
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# make the cells square so the pitch of wordlines will match bitlines
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print("height: {0} width: {1}".format(height, width))
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if width > height:
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self.width = width
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self.height = width
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else:
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self.width = height
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self.height = height
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super().add_boundary()
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def add_poly(self):
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poly_x = 0.5 * (self.nmos.poly_height + self.poly_extend_active_spacing)
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# 0.5 * self.nmos.contact_width + self.contact_to_gate
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self.poly = self.add_rect_center("poly", vector(poly_x, self.base_width * 0.5), 2 * poly_x, self.poly_width)
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def add_metal(self):
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if self.route_layer == "li":
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via = "mcon"
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else:
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via = "via{}".format(self.route_layer[len(self.route_layer) - 1])
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wire_y = self.height + drc["minwidth_{}".format(via)] * 0.5
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wire_x = 0.5 * (self.width - self.poly_extend_active_spacing)
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wire_start = vector( wire_x, 0)
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wire_end = vector(wire_x, wire_y)
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# if self.route_layer == 'm1':
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# if self.drain_contact:
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# self.add_via_center(self.li_stack, [wire_x, wire_y])
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# if self.source_contact:
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# self.add_via_center(self.li_stack, [self.width, wire_y])
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self.add_path(self.route_layer, [wire_start, wire_end])
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# drain_x = 0
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# drain_y = 0.5 * (self.width)
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source_x = 0.5 * (self.width - self.poly_extend_active_spacing)
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source_y = 0
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source_pos = vector(source_x, source_y)
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self.add_layout_pin_rect_center("S", self.route_layer, source_pos)
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drain_pos = vector(source_x, self.height)
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self.add_layout_pin_rect_center("D", self.route_layer, drain_pos)
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def add_nmos(self):
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#used only for layout constants
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# if not self.source_contact:
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# add_source = False
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# else:
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# add_source = self.route_layer
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# if not self.drain_contact:
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# add_drain = False
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# else:
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# add_drain = self.route_layer
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self.nmos = factory.create(module_type="ptx",
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module_name="nmos_rom_mod",
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tx_type="nmos",
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add_source_contact=self.add_source_contact,
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add_drain_contact=self.add_drain_contact
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)
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