mirror of https://github.com/VLSIDA/OpenRAM.git
283 lines
9.8 KiB
Python
283 lines
9.8 KiB
Python
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from math import ceil, log, sqrt
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from openram.base import vector
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from openram.base import design
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from openram import OPTS
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from openram.sram_factory import factory
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from openram.tech import drc
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class rom_base_bank(design):
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def __init__(self, strap_spacing=0, data_file=None, name="", word_size=2) -> None:
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# self.cols = word_size * 8
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self.read_binary(word_size=word_size, data_file=data_file)
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self.num_outputs = self.rows
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self.num_inputs = ceil(log(self.rows, 2))
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# self.data = [[0, 1, 0, 1], [1, 1, 1, 1], [1, 1, 0, 0], [0, 0, 1, 0]]
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self.strap_spacing = strap_spacing
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self.route_layer = "li"
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self.bus_layer = "m2"
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self.interconnect_layer = "m1"
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super().__init__(name=name)
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self.setup_layout_constants()
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self.create_netlist()
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self.create_layout()
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"""
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Reads a hexadecimal file from a given directory to be used as the data written to the ROM
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endian is either "big" or "little"
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word_size is the number of bytes per word
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sets the row and column size based on the size of binary input, tries to keep array as square as possible,
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"""
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def read_binary(self, data_file, word_size=2, endian="big"):
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hex_file = open(data_file, 'r')
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hex_data = hex_file.read()
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bin_data = list("{0:08b}".format(int(hex_data, 16)))
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bin_data = [int(x) for x in bin_data]
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# data size in bytes
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data_size = len(bin_data) / 8
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num_words = int(data_size / word_size)
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bytes_per_col = sqrt(num_words)
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self.words_per_row = int(ceil(bytes_per_col /(2*word_size)))
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bits_per_row = self.words_per_row * word_size * 8
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chunked_data = []
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for i in range(0, len(bin_data), bits_per_row):
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word = bin_data[i:i + bits_per_row]
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if len(word) < bits_per_row:
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word = [0] * (bits_per_row - len(word)) + word
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chunked_data.append(word)
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if endian == "big":
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chunked_data.reverse()
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self.data = chunked_data
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self.cols = bits_per_row
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self.rows = int(num_words / (self.words_per_row))
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# print("hex: {0}, binary: {1}, chunked: {2}".format(hex_data, bin_data, chunked_data))
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def create_netlist(self):
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self.add_modules()
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# self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_instances()
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# self.channel_route()
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self.route_decode_outputs()
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self.route_control()
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self.route_supplies()
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self.height = self.array_inst.height
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self.width = self.array_inst.width
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self.add_boundary()
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def setup_layout_constants(self):
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self.route_layer_width = drc["minwidth_{}".format(self.route_layer)]
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self.route_layer_pitch = drc["{0}_to_{0}".format(self.route_layer)]
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self.bus_layer_width = drc["minwidth_{}".format(self.bus_layer)]
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self.bus_layer_pitch = drc["{0}_to_{0}".format(self.bus_layer)]
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self.interconnect_layer_width = drc["minwidth_{}".format(self.interconnect_layer)]
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self.interconnect_layer_pitch = drc["{0}_to_{0}".format(self.interconnect_layer)]
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def add_pins(self):
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self.add_pin("READ", "INPUT")
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self.add_pin("CS", "INPUT")
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for i in range(self.num_inputs):
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self.add_pin("addr_{}".format(i), "INPUT")
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out_pins = []
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for j in range(self.num_outputs):
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out_pins.append("rom_out_{}".format(j))
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self.add_pin_list(out_pins, "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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self.array = factory.create(module_type="rom_base_array", cols=self.cols, rows=self.rows, strap_spacing=self.strap_spacing, bitmap=self.data, route_layer=self.route_layer, pitch_match=True)
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self.decode_array = factory.create(module_type="rom_decoder", num_outputs=self.rows, strap_spacing=self.strap_spacing, route_layer=self.route_layer)
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self.control_logic = factory.create(module_type="rom_control_logic", num_outputs=(self.rows + self.cols) / 2, height=self.decode_array.inv_inst.height)
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def create_instances(self):
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array_pins = []
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decode_pins = []
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for bl in range(self.cols):
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name = "bl_{}".format(bl)
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array_pins.append(name)
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for wl in range(self.rows):
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name = "wl_{}".format(wl)
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array_pins.append(wl)
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array_pins.append("precharge")
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array_pins.append("vdd")
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array_pins.append("gnd")
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for addr in range(self.num_inputs):
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name = "addr_{}".format(addr)
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decode_pins.append(name)
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for wl in range(self.rows):
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name = "wl_{}".format(wl)
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decode_pins.append(name)
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decode_pins.append("precharge")
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decode_pins.append("vdd")
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decode_pins.append("gnd")
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self.array_inst = self.add_inst(name="rom_bit_array", mod=self.array)
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self.connect_inst(array_pins)
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self.decode_inst = self.add_inst(name="rom_decoder", mod=self.decode_array)
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self.connect_inst(decode_pins)
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self.control_inst = self.add_inst(name="rom_control", mod=self.control_logic)
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self.connect_inst(["READ", "CS", "precharge", "vdd", "gnd"])
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def place_instances(self):
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array_x = self.decode_inst.width + (2) * ( self.route_layer_width + self.route_layer_pitch )
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array_y = self.decode_array.inv_inst.height - self.array.precharge_inst.cy() - self.array.dummy.height * 0.5
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self.array_offset = vector(array_x ,array_y)
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self.decode_offset = vector(0, 0)
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self.control_offset = vector(0,0)
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self.array_inst.place(offset=self.array_offset)
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self.decode_inst.place(offset=self.decode_offset)
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self.control_inst.place(offset=self.control_offset, mirror="MX")
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def create_wl_bus(self):
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bus_x = self.decode_inst.width + ( drc["minwidth_{}".format(self.bus_layer)] + 1.5 * drc["{0}_to_{0}".format(self.bus_layer)] )
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bus_y = self.array_inst.by() + self.bus_layer_pitch + self.bus_layer_width
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self.wl_interconnects = []
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for wl in range(self.rows):
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self.wl_interconnects.append("wl_interconnect_{}".format(wl))
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self.wl_bus = self.create_vertical_bus(self.bus_layer, vector(bus_x, bus_y), self.wl_interconnects, self.decode_inst.uy() - self.array_inst.by() )
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def route_decode_outputs(self):
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for wl in range(self.rows):
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decode_output = self.decode_array.output_names[wl]
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decode_out_pin = self.decode_inst.get_pin(decode_output)
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array_wl = self.array.wordline_names[0][wl]
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array_wl_pin = self.array_inst.get_pin(array_wl)
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# wl_bus_wire = self.wl_bus[self.wl_interconnects[wl]]
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start = decode_out_pin.center()
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end = vector(array_wl_pin.cx(), start.y)
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self.add_segment_center(self.bus_layer, start, end)
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self.add_via_stack_center(array_wl_pin.center(), self.bus_layer, self.interconnect_layer )
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def route_array_inputs(self):
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for wl in range(self.rows):
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array_wl = self.array.wordline_names[0][wl]
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array_wl_pin = self.array_inst.get_pin(array_wl)
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wl_bus_wire = self.wl_bus[self.wl_interconnects[wl]]
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end = array_wl_pin.center()
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start = vector(wl_bus_wire.cx(), end.y)
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self.add_segment_center(self.interconnect_layer, start, end)
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self.add_via_stack_center(start, self.route_layer, self.interconnect_layer )
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def channel_route(self):
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route_nets = []
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for wl in range(self.rows):
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array_wl = self.array.wordline_names[0][wl]
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array_wl_pin = self.array_inst.get_pin(array_wl)
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decode_output = self.decode_array.output_names[wl]
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decode_out_pin = self.decode_inst.get_pin(decode_output)
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route_nets.append([array_wl_pin, decode_out_pin])
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array_prechrg = self.array_inst.get_pin("precharge")
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decode_prechrg = self.decode_inst.get_pin("precharge")
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route_nets.append([array_prechrg, decode_prechrg])
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channel_start = vector(decode_out_pin.cx(), self.decode_array.array_inst.by())
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channel = self.create_vertical_channel_route(netlist=route_nets, offset=channel_start, layer_stack=self.m1_stack, directions="nonpref")
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def route_control(self):
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prechrg_control = self.control_inst.get_pin("prechrg")
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decode_prechrg = self.decode_inst.get_pin("precharge")
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array_prechrg = self.array_inst.get_pin("precharge")
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end = vector(decode_prechrg.cx() - 0.5 * self.interconnect_layer_width, prechrg_control.cy())
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self.add_segment_center(self.interconnect_layer, prechrg_control.center(), end)
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start = end + vector(0.5 * self.interconnect_layer_width, 0)
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self.add_segment_center(self.interconnect_layer, start, decode_prechrg.center())
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def route_supplies(self):
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gnd_start = vector(self.array_inst.get_pins("gnd")[0].cx(),0)
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decode_gnd = self.decode_inst.get_pin("gnd")
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decode_vdd = self.decode_inst.get_pin("vdd")
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array_vdd = self.array_inst.get_pin("vdd")
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# self.add_segment_center("m1", gnd_start, decode_gnd.center())
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self.add_power_pin("gnd", decode_vdd.center())
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self.add_power_pin("vdd", decode_gnd.center())
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vdd_start = vector(array_vdd.lx() + 0.5 * self.via1_space, array_vdd.cy())
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end = vector(decode_vdd.lx(), vdd_start.y)
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self.add_segment_center(self.interconnect_layer, vdd_start, end)
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self.add_via_stack_center(vdd_start, "m1", self.interconnect_layer)
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vdd_start = vector(decode_vdd.cx(), vdd_start.y)
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self.add_segment_center(self.interconnect_layer, vdd_start, decode_vdd.center())
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