Sam Crow cd1b0f973d Revert pin/net spice object work ...

This reverts commits 01116 6e3e9 2ced8 c67fd 2b9e7 bfabe 09aa3 5907c aa717 478c7 45b88 d0339 e15fe 7581d c8c43 146ef

2023-08-14 18:44:51 -07:00

..

__init__.py

Verilog ROM model created for testing

2023-06-12 15:35:54 -07:00

channel_route.py

Update copyright year

2023-01-28 22:56:27 -08:00

contact.py

Revert pin/net spice object work

2023-08-14 18:44:51 -07:00

delay_data.py

Update copyright year

2023-01-28 22:56:27 -08:00

design.py

Revert pin/net spice object work

2023-08-14 18:44:51 -07:00

errors.py

Update copyright year

2023-01-28 22:56:27 -08:00

geometry.py

Revert pin/net spice object work

2023-08-14 18:44:51 -07:00

hierarchy_design.py

Revert pin/net spice object work

2023-08-14 18:44:51 -07:00

hierarchy_layout.py

Revert pin/net spice object work

2023-08-14 18:44:51 -07:00

hierarchy_spice.py

Revert pin/net spice object work

2023-08-14 18:44:51 -07:00

lef.py

Revert pin/net spice object work

2023-08-14 18:44:51 -07:00

logical_effort.py

Update copyright year

2023-01-28 22:56:27 -08:00

pin_layout.py

Update copyright year

2023-01-28 22:56:27 -08:00

power_data.py

Update copyright year

2023-01-28 22:56:27 -08:00

rom_verilog.py

Fixed formatting on all files

2023-06-14 12:28:36 -07:00

route.py

Update copyright year

2023-01-28 22:56:27 -08:00

timing_graph.py

Update copyright year

2023-01-28 22:56:27 -08:00

utils.py

Update copyright year

2023-01-28 22:56:27 -08:00

vector3d.py

Update copyright year

2023-01-28 22:56:27 -08:00

vector.py

Update copyright year

2023-01-28 22:56:27 -08:00

verilog.py

Update copyright year

2023-01-28 22:56:27 -08:00

wire_path.py

Update copyright year

2023-01-28 22:56:27 -08:00

wire_spice_model.py

add fixme note for unit conversion

2023-06-28 14:05:42 -07:00

wire.py

Update copyright year

2023-01-28 22:56:27 -08:00