mirror of https://github.com/VLSIDA/OpenRAM.git
420 lines
18 KiB
Python
420 lines
18 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
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# All rights reserved.
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#
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from openram import debug
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from openram.base import vector
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from openram.base import contact
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from openram.sram_factory import factory
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from openram.tech import drc, spice
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from openram.tech import cell_properties as props
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from openram import OPTS
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from .bitcell_base_array import bitcell_base_array
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class replica_bitcell_array(bitcell_base_array):
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"""
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Creates a bitcell array of cols x rows and then adds the replica
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and dummy columns and rows. Replica columns are on the left and
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right, respectively and connected to the given bitcell ports.
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Dummy are the outside columns/rows with WL and BL tied to gnd.
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Requires a regular bitcell array, replica bitcell, and dummy
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bitcell (BL/BR disconnected).
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"""
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def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
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super().__init__(name=name, rows=rows, cols=cols, column_offset=0)
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debug.info(1, "Creating {0} {1} x {2} rbls: {3} left_rbl: {4} right_rbl: {5}".format(self.name,
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rows,
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cols,
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rbl,
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left_rbl,
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right_rbl))
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self.add_comment("rows: {0} cols: {1}".format(rows, cols))
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self.add_comment("rbl: {0} left_rbl: {1} right_rbl: {2}".format(rbl, left_rbl, right_rbl))
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self.column_size = cols
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self.row_size = rows
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# This is how many RBLs are in all the arrays
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self.rbl = rbl
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# This specifies which RBL to put on the left or right by port number
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# This could be an empty list
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if left_rbl is not None:
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self.left_rbl = left_rbl
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else:
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self.left_rbl = []
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# This could be an empty list
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if right_rbl is not None:
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self.right_rbl = right_rbl
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else:
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self.right_rbl=[]
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self.rbls = self.left_rbl + self.right_rbl
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debug.check(sum(self.rbl) >= len(self.left_rbl) + len(self.right_rbl),
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"Invalid number of RBLs for port configuration.")
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def add_modules(self):
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""" Array and dummy/replica columns
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d or D = dummy cell (caps to distinguish grouping)
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r or R = replica cell (caps to distinguish grouping)
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b or B = bitcell
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replica columns 1
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v v
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bdDDDDDDDDDDDDDDdb <- Dummy row
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bdDDDDDDDDDDDDDDrb <- Dummy row
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br--------------rb
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br| Array |rb
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br| row x col |rb
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br--------------rb
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brDDDDDDDDDDDDDDdb <- Dummy row
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bdDDDDDDDDDDDDDDdb <- Dummy row
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^^^^^^^^^^^^^^^
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dummy rows cols x 1
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^ dummy columns ^
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1 x (rows + 4)
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"""
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# Bitcell array
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self.bitcell_array = factory.create(module_type="bitcell_array",
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column_offset=1 + len(self.left_rbl),
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cols=self.column_size,
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rows=self.row_size)
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# Replica bitlines
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self.replica_columns = {}
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for port in self.all_ports:
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if port in self.left_rbl:
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# We will always have self.rbl[0] rows of replica wordlines below
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# the array.
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# These go from the top (where the bitcell array starts ) down
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replica_bit = self.rbl[0] - port - 1
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column_offset = len(self.left_rbl)
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elif port in self.right_rbl:
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# We will always have self.rbl[0] rows of replica wordlines below
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# the array.
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# These go from the bottom up
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replica_bit = self.rbl[0] + self.row_size + port - 1
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column_offset = len(self.left_rbl) + self.column_size + 1
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else:
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continue
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self.replica_columns[port] = factory.create(module_type="replica_column",
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rows=self.row_size,
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rbl=self.rbl,
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column_offset=column_offset,
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replica_bit=replica_bit)
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# Dummy row
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self.dummy_row = factory.create(module_type="dummy_array",
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column
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column_offset=1 + len(self.left_rbl),
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mirror=0)
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def add_pins(self):
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# Arrays are always:
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# bitlines (column first then port order)
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# word lines (row first then port order)
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# dummy wordlines
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# replica wordlines
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# regular wordlines (bottom to top)
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# # dummy bitlines
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# replica bitlines (port order)
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# regular bitlines (left to right port order)
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#
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# vdd
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# gnd
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self.add_bitline_pins()
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self.add_wordline_pins()
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_bitline_pins(self):
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# The bit is which port the RBL is for
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for bit in self.rbls:
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for port in self.all_ports:
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self.rbl_bitline_names[bit].append("rbl_bl_{0}_{1}".format(port, bit))
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for port in self.all_ports:
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self.rbl_bitline_names[bit].append("rbl_br_{0}_{1}".format(port, bit))
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# Make a flat list too
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self.all_rbl_bitline_names = [x for sl in self.rbl_bitline_names for x in sl]
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self.bitline_names = self.bitcell_array.bitline_names
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# Make a flat list too
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self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
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self.bitline_pin_list = []
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for port in self.left_rbl:
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self.bitline_pin_list.extend(self.rbl_bitline_names[port])
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self.bitline_pin_list.extend(self.all_bitline_names)
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for port in self.right_rbl:
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self.bitline_pin_list.extend(self.rbl_bitline_names[port])
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self.add_pin_list(self.bitline_pin_list, "INOUT")
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def add_wordline_pins(self):
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# Unused wordlines are connected to ground at the next level of hierarchy
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self.unused_wordline_names = []
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for port in self.all_ports:
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for bit in self.all_ports:
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self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit))
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if bit != port:
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self.unused_wordline_names.append("rbl_wl_{0}_{1}".format(port, bit))
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self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl]
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self.wordline_names = self.bitcell_array.wordline_names
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self.all_wordline_names = self.bitcell_array.all_wordline_names
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# All wordlines including RBL
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self.wordline_pin_list = []
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for bit in range(self.rbl[0]):
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self.wordline_pin_list.extend(self.rbl_wordline_names[bit])
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self.wordline_pin_list.extend(self.all_wordline_names)
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for bit in range(self.rbl[1]):
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self.wordline_pin_list.extend(self.rbl_wordline_names[self.rbl[0] + bit])
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self.used_wordline_names = []
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for port in range(self.rbl[0]):
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self.used_wordline_names.append(self.rbl_wordline_names[port][port])
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self.used_wordline_names.extend(self.all_wordline_names)
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for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
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self.used_wordline_names.append(self.rbl_wordline_names[port][port])
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self.add_pin_list(self.wordline_pin_list, "INPUT")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.supplies = ["vdd", "gnd"]
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# Main array
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self.bitcell_array_inst=self.add_inst(name="bitcell_array",
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mod=self.bitcell_array)
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self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies)
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# Replica columns
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self.replica_col_insts = []
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for port in self.all_ports:
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if port in self.rbls:
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self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
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mod=self.replica_columns[port]))
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self.connect_inst(self.rbl_bitline_names[port] + self.wordline_pin_list + self.supplies)
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else:
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self.replica_col_insts.append(None)
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# Dummy rows above/below the bitcell array (connected with the replica cell wl)
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self.dummy_row_replica_insts = []
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# Note, this is the number of left and right even if we aren't adding the columns to this bitcell array!
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for port in self.all_ports: # TODO: tie to self.rbl or whatever
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self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
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mod=self.dummy_row))
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self.connect_inst(self.all_bitline_names + self.rbl_wordline_names[port] + self.supplies)
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def create_layout(self):
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# This creates space for the unused wordline connections as well as the
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# row-based or column based power and ground lines.
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self.vertical_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[0]))
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self.horizontal_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[2]))
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# This is a bitcell x bitcell offset to scale
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self.bitcell_offset = vector(self.cell.width, self.cell.height)
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self.col_end_offset = vector(self.cell.width, self.cell.height)
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self.row_end_offset = vector(self.cell.width, self.cell.height)
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# Everything is computed with the main array
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self.bitcell_array_inst.place(offset=0)
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self.add_replica_columns()
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# Array was at (0, 0) but move everything so it is at the lower left
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# We move DOWN the number of left RBL even if we didn't add the column to this bitcell array
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# Note that this doesn't include the row/col cap
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array_offset = self.bitcell_offset.scale(len(self.left_rbl), self.rbl[0])
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self.translate_all(array_offset.scale(-1, -1))
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self.add_layout_pins()
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self.route_supplies()
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self.height = (sum(self.rbl) + self.row_size) * self.cell.height
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self.width = (len(self.rbls) + self.column_size) * self.cell.width
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self.add_boundary()
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self.DRC_LVS()
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def get_main_array_top(self):
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""" Return the top of the main bitcell array. """
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return self.bitcell_array_inst.uy()
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def get_main_array_bottom(self):
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""" Return the bottom of the main bitcell array. """
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return self.bitcell_array_inst.by()
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def get_main_array_left(self):
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""" Return the left of the main bitcell array. """
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return self.bitcell_array_inst.lx()
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def get_main_array_right(self):
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""" Return the right of the main bitcell array. """
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return self.bitcell_array_inst.rx()
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def get_column_offsets(self):
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"""
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Return an array of the x offsets of all the regular bits
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"""
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offsets = [x + self.bitcell_array_inst.lx() for x in self.bitcell_array.get_column_offsets()]
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return offsets
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def add_replica_columns(self):
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""" Add replica columns on left and right of array """
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# Grow from left to right, toward the array
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for bit, port in enumerate(self.left_rbl):
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offset = self.bitcell_offset.scale(-len(self.left_rbl) + bit, -self.rbl[0])
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self.replica_col_insts[bit].place(offset)
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# Grow to the right of the bitcell array, array outward
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for bit, port in enumerate(self.right_rbl):
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offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.rbl[0])
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self.replica_col_insts[self.rbl[0] + bit].place(offset)
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# Replica dummy rows
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# Add the dummy rows even if we aren't adding the replica column to this bitcell array
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# These grow up, toward the array
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for bit in range(self.rbl[0]):
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dummy_offset = self.bitcell_offset.scale(0, -self.rbl[0] + bit + (-self.rbl[0] + bit) % 2)
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self.dummy_row_replica_insts[bit].place(offset=dummy_offset,
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mirror="MX" if (-self.rbl[0] + bit) % 2 else "R0")
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# These grow up, away from the array
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for bit in range(self.rbl[1]):
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dummy_offset = self.bitcell_offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul()
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self.dummy_row_replica_insts[self.rbl[0] + bit].place(offset=dummy_offset,
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mirror="MX" if (self.row_size + bit) % 2 else "R0")
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def add_layout_pins(self):
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""" Add the layout pins """
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# All wordlines
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# Main array wl
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for pin_name in self.all_wordline_names:
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pin_list = self.bitcell_array_inst.get_pins(pin_name)
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for pin in pin_list:
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin.ll().scale(0, 1),
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width=self.width,
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height=pin.height())
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# Replica wordlines (go by the row instead of replica column because we may have to add a pin
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# even though the column is in another local bitcell array)
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for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
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for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
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pin = inst.get_pin(pin_name)
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self.add_layout_pin(text=wl_name,
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layer=pin.layer,
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offset=pin.ll().scale(0, 1),
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width=self.width,
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height=pin.height())
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# Main array bl/br
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for pin_name in self.all_bitline_names:
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pin_list = self.bitcell_array_inst.get_pins(pin_name)
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for pin in pin_list:
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin.ll().scale(1, 0),
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width=pin.width(),
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height=self.height)
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# Replica bitlines
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if len(self.rbls) > 0:
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for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts):
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pin_names = self.replica_columns[self.rbls[0]].all_bitline_names
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for (bl_name, pin_name) in zip(names, pin_names):
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pin = inst.get_pin(pin_name)
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self.add_layout_pin(text=bl_name,
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layer=pin.layer,
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offset=pin.ll().scale(1, 0),
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width=pin.width(),
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height=self.height)
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def route_supplies(self):
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for inst in self.insts:
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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def analytical_power(self, corner, load):
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"""Power of Bitcell array and bitline in nW."""
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# Dynamic Power from Bitline
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bl_wire = self.gen_bl_wire()
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cell_load = 2 * bl_wire.return_input_cap()
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bl_swing = OPTS.rbl_delay_percentage
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freq = spice["default_event_frequency"]
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bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
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# Calculate the bitcell power which currently only includes leakage
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cell_power = self.cell.analytical_power(corner, load)
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# Leakage power grows with entire array and bitlines.
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total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
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cell_power.leakage * self.column_size * self.row_size)
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return total_power
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def gen_bl_wire(self):
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if OPTS.netlist_only:
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height = 0
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else:
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height = self.height
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bl_pos = 0
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bl_wire = self.generate_rc_net(int(self.row_size - bl_pos), height, drc("minwidth_m1"))
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bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
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return bl_wire
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def graph_exclude_bits(self, targ_row=None, targ_col=None):
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"""
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Excludes bits in column from being added to graph except target
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"""
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self.bitcell_array.graph_exclude_bits(targ_row, targ_col)
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def graph_exclude_replica_col_bits(self):
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"""
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Exclude all replica/dummy cells in the replica columns except the replica bit.
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"""
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for port in self.left_rbl + self.right_rbl:
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self.replica_columns[port].exclude_all_but_replica()
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def get_cell_name(self, inst_name, row, col):
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"""
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Gets the spice name of the target bitcell.
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"""
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return self.bitcell_array.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.bitcell_array_inst.name, row, col)
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def clear_exclude_bits(self):
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"""
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Clears the bit exclusions
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"""
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self.bitcell_array.init_graph_params()
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