mirror of https://github.com/VLSIDA/OpenRAM.git
160 lines
6.7 KiB
Python
160 lines
6.7 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2022 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import math
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from openram import debug
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from openram.base import design
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from openram.base import vector
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from openram.sram_factory import factory
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from openram import OPTS
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class write_mask_and_array(design):
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"""
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Array of AND gates to turn write mask signal on only when w_en is on.
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The write mask AND array goes between the write driver array and the sense amp array.
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"""
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def __init__(self, name, columns, word_size, write_size, offsets=None, column_offset=0):
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super().__init__(name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("columns: {0}".format(columns))
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self.add_comment("word_size {0}".format(word_size))
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self.add_comment("write_size {0}".format(write_size))
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self.columns = columns
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self.word_size = word_size
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self.write_size = write_size
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self.offsets = offsets
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self.column_offset = column_offset
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self.words_per_row = int(columns / word_size)
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self.num_wmasks = int(math.ceil(word_size / write_size))
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_and2_array()
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def create_layout(self):
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self.place_and2_array()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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for bit in range(self.num_wmasks):
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self.add_pin("wmask_in_{}".format(bit), "INPUT")
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self.add_pin("en", "INPUT")
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for bit in range(self.num_wmasks):
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self.add_pin("wmask_out_{}".format(bit), "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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# Size the AND gate for the number of write drivers it drives, which is equal to the write size.
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# Assume stage effort of 3 to compute the size
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self.and2 = factory.create(module_type="pand2",
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size=max(self.write_size / 4.0, 1))
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def create_and2_array(self):
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self.and2_insts = {}
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for bit in range(self.num_wmasks):
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name = "and2_{}".format(bit)
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self.and2_insts[bit] = self.add_inst(name=name,
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mod=self.and2)
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self.connect_inst(["wmask_in_{}".format(bit),
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"en",
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"wmask_out_{}".format(bit),
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"vdd", "gnd"])
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def place_and2_array(self):
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# Place the write mask AND array at the start of each write driver enable length.
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# This ensures the write mask AND array will be directly under the corresponding write driver enable wire.
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# This is just used for measurements, so don't add the module
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self.bitcell = factory.create(module_type=OPTS.bitcell)
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self.driver = factory.create(module_type="write_driver")
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if self.bitcell.width > self.driver.width:
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self.driver_spacing = self.bitcell.width
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else:
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self.driver_spacing = self.driver.width
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self.wmask_en_len = self.words_per_row * (self.write_size * self.driver_spacing)
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debug.check(self.wmask_en_len >= self.and2.width,
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"Write mask AND is wider than the corresponding write drivers {0} vs {1}.".format(self.and2.width,
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self.wmask_en_len))
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if not self.offsets:
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self.offsets = []
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for i in range(self.columns):
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self.offsets.append((i + self.write_size - 1) * self.driver_spacing)
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self.width = self.offsets[-1] + self.bitcell.width
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self.height = self.and2.height
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write_bits = self.columns / self.num_wmasks
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for i in range(self.num_wmasks):
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base = vector(self.offsets[int(i * write_bits)], 0)
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self.and2_insts[i].place(base)
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def add_layout_pins(self):
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# Create the enable pin that connects all write mask AND array's B pins
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en_pin = self.and2_insts[0].get_pin("B")
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self.add_layout_pin_segment_center(text="en",
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layer="m3",
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start=vector(0, en_pin.cy()),
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end=vector(self.width, en_pin.cy()))
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for i in range(self.num_wmasks):
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# Route the A pin over to the left so that it doesn't conflict with the sense
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# amp output which is usually in the center
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inst = self.and2_insts[i]
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a_pin = inst.get_pin("A")
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a_pos = a_pin.center()
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in_pos = vector(inst.lx(),
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a_pos.y)
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self.add_via_stack_center(from_layer=a_pin.layer,
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to_layer="m2",
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offset=in_pos)
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self.add_layout_pin_rect_center(text="wmask_in_{0}".format(i),
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layer="m2",
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offset=in_pos)
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self.add_path(a_pin.layer, [in_pos, a_pos])
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# Copy remaining layout pins
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self.copy_layout_pin(inst, "Z", "wmask_out_{0}".format(i))
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# Add via connections to metal3 for AND array's B pin
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en_pin = inst.get_pin("B")
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en_pos = en_pin.center()
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self.add_via_stack_center(from_layer=en_pin.layer,
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to_layer="m3",
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offset=en_pos)
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# Add connection to the supply
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for supply_name in ["gnd", "vdd"]:
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supply_pin = inst.get_pin(supply_name)
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self.add_via_stack_center(from_layer=supply_pin.layer,
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to_layer="m1",
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offset=supply_pin.center())
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for supply in ["gnd", "vdd"]:
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supply_pin = self.and2_insts[0].get_pin(supply)
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supply_pin_yoffset = supply_pin.cy()
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left_loc = vector(0, supply_pin_yoffset)
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right_loc = vector(self.width, supply_pin_yoffset)
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self.add_path("m1", [left_loc, right_loc])
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for loc in [left_loc, right_loc]:
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self.add_via_stack_center(from_layer=supply_pin.layer,
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to_layer="m1",
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offset=loc)
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self.copy_power_pin(supply_pin, loc=loc)
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