mirror of https://github.com/VLSIDA/OpenRAM.git
42 lines
1.4 KiB
Python
42 lines
1.4 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2022 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram.base import design
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from openram.tech import cell_properties as props
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from openram.tech import spice
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class dff(design):
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"""
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Memory address flip-flop
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"""
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def __init__(self, name="dff"):
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super().__init__(name, prop=props.dff)
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_frequency"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["dff_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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c_para = spice["dff_out_cap"] # ff
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transition_prob = 0.5
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return transition_prob * (c_load + c_para)
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges based on inputs/outputs. Overrides base class function."""
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self.add_graph_edges(graph, port_nets)
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