mirror of https://github.com/VLSIDA/OpenRAM.git
50 lines
1.4 KiB
Python
Executable File
50 lines
1.4 KiB
Python
Executable File
#!/usr/bin/env python3
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"Run a regresion test the library cells for DRC"
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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import debug
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OPTS = globals.OPTS
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class no_blockages_test(openram_test):
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"""
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Simplest two pin route test with no blockages.
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"""
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def runTest(self):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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from supply_router import supply_router as router
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if False:
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from control_logic import control_logic
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cell = control_logic(16)
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layer_stack =("metal3","via3","metal4")
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rtr=router(layer_stack, cell)
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self.assertTrue(rtr.route())
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else:
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from sram import sram
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from sram_config import sram_config
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c = sram_config(word_size=4,
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num_words=32,
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num_banks=1)
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c.words_per_row=1
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sram = sram(c, "sram1")
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cell = sram.s
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self.local_check(cell,True)
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# fails if there are any DRC errors on any cells
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globals.end_openram()
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# instantiate a copy of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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