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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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cc0be510c75cd534e1312caf785f7297af43effc
OpenRAM/compiler/pgates
T
History
Hunter Nichols 6152ec7ec5 Merge branch 'dev' into multiport_characterization
2019-01-15 16:33:39 -08:00
..
pand2.py
Changed s_en delay calculation based recent control logic changes.
2018-12-05 17:10:11 -08:00
pbuf.py
Changed s_en delay calculation based recent control logic changes.
2018-12-05 17:10:11 -08:00
pdriver.py
Added height to init in pdriver.py
2018-12-13 19:03:31 -08:00
pgate.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
pinv.py
Made parasitic delay parameter in Freepdk45 more accurate, added stage names to delay model.
2018-12-17 23:32:02 -08:00
pinvbuf.py
Separated relative delay into rise/fall.
2018-11-14 23:34:53 -08:00
pnand2.py
Made parasitic delay parameter in Freepdk45 more accurate, added stage names to delay model.
2018-12-17 23:32:02 -08:00
pnand3.py
Made parasitic delay parameter in Freepdk45 more accurate, added stage names to delay model.
2018-12-17 23:32:02 -08:00
pnor2.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
precharge.py
Merged with dev. Fixed conflicts in tests.
2018-12-02 23:09:00 -08:00
ptx.py
Merged with dev. Fixed conflicts in tests.
2018-12-02 23:09:00 -08:00
single_level_column_mux.py
Merge branch 'dev' into multiport_layout
2018-11-08 18:00:28 -08:00
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