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OpenRAM
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OpenRAM/compiler/modules
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Matt Guthaus 3539887ee4 Updating ms_flop removal. 
Updated characterizer for dff.
Added new setup/hold results for dff instead of ms_flop.
Removed ms_flop references in sram-base.
Fixed syntax errors in SCN3ME tech file.
 		2018-09-13 11:40:24 -07:00
..
bank.py Updating ms_flop removal. 2018-09-13 11:40:24 -07:00
bank_select.py Move place function to instance class rather than hierarchy. 2018-08-27 17:25:39 -07:00
bitcell.py Merging latest changes from multiport with changes made to pbitcell. Changing select code from other modules and tests to reflect changes made to pbitcell. 2018-09-06 19:36:50 -07:00
bitcell_array.py Clean up new code for add_modules, add_pins and netlist/layouts. 2018-08-28 10:24:09 -07:00
control_logic.py add trailing 0 to web 2018-09-09 15:16:53 -07:00
delay_chain.py Make bitcell width/height not static. Update modules to use it for pbitcell. 2018-09-04 11:55:22 -07:00
dff.py Remove ms_flop and replace with dff. Might break setup_hold tests. 2018-09-13 11:02:28 -07:00
dff_array.py Clean up new code for add_modules, add_pins and netlist/layouts. 2018-08-28 10:24:09 -07:00
dff_buf.py Clean up new code for add_modules, add_pins and netlist/layouts. 2018-08-28 10:24:09 -07:00
dff_buf_array.py Clean up new code for add_modules, add_pins and netlist/layouts. 2018-08-28 10:24:09 -07:00
dff_inv.py Clean up new code for add_modules, add_pins and netlist/layouts. 2018-08-28 10:24:09 -07:00
dff_inv_array.py Found rotate bug in transformCoordinate. Cleaned up transFlags. 2018-09-04 16:35:40 -07:00
hierarchical_decoder.py Make bitcell width/height not static. Update modules to use it for pbitcell. 2018-09-04 11:55:22 -07:00
hierarchical_predecode.py Move place function to instance class rather than hierarchy. 2018-08-27 17:25:39 -07:00
hierarchical_predecode2x4.py Converted all modules to not run create_layout when netlist_only 2018-08-27 16:42:48 -07:00
hierarchical_predecode3x8.py Converted all modules to not run create_layout when netlist_only 2018-08-27 16:42:48 -07:00
multibank.py Updating ms_flop removal. 2018-09-13 11:40:24 -07:00
precharge_array.py Clean up new code for add_modules, add_pins and netlist/layouts. 2018-08-28 10:24:09 -07:00
replica_bitcell.py Finish renaming replica bitcell and bitline pin names. 2018-09-04 14:03:15 -07:00
replica_bitline.py Generalized wl names using bitcell's list_all_wl_names function to accomodate multiport 2018-09-09 22:42:52 -07:00
sense_amp.py Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
sense_amp_array.py Make bitcell width/height not static. Update modules to use it for pbitcell. 2018-09-04 11:55:22 -07:00
single_level_column_mux_array.py Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary. 2018-09-09 22:06:29 -07:00
tri_gate.py Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
tri_gate_array.py Clean up new code for add_modules, add_pins and netlist/layouts. 2018-08-28 10:24:09 -07:00
wordline_driver.py Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary. 2018-09-09 22:06:29 -07:00
write_driver.py Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
write_driver_array.py Make bitcell width/height not static. Update modules to use it for pbitcell. 2018-09-04 11:55:22 -07:00